| Message ID | 1458052809-23426-11-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote: > [ text/plain ] > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > On VLV at least, the BIOS may leave the DSI PLL enabled in some wonky > state where it just refuses to lock. Simply disabling the PLL before > reconfiguring it is not enough to fix it, but power gating the PLL > prior to reconfiguring does work. > > This happens on BYT FFRD8 when booting with HDMI connected so the DSI > display will not be lit up by the BIOS. > > Also we can remove the code for BXT that disables the PLL before > enabling it again. > > v2: s/vlv/intel/ since BXT made thing generic > v3: Remove the BXT disable PLL before enable trick > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++ > drivers/gpu/drm/i915/intel_dsi_pll.c | 8 -------- > 2 files changed, 6 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index 4023b6bffa47..787411e1c36f 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -482,7 +482,13 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) > > DRM_DEBUG_KMS("\n"); > > + /* > + * The BIOS may leave the PLL in a wonky state where it doesn't > + * lock. It needs to be fully powered down to fix it. > + */ > + intel_disable_dsi_pll(encoder); > intel_enable_dsi_pll(encoder); > + > intel_dsi_prepare(encoder); > > /* Panel Enable over CRC PMIC */ > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c > index 916cc92c1400..978cc2668a3d 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c > @@ -474,14 +474,6 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder) > > DRM_DEBUG_KMS("\n"); > > - val = I915_READ(BXT_DSI_PLL_ENABLE); > - > - if (val & BXT_DSI_PLL_DO_ENABLE) { > - WARN(1, "DSI PLL already enabled. Disabling it.\n"); > - val &= ~BXT_DSI_PLL_DO_ENABLE; > - I915_WRITE(BXT_DSI_PLL_ENABLE, val); > - } > - > /* Configure PLL vales */ > if (!bxt_configure_dsi_pll(encoder)) { > DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 4023b6bffa47..787411e1c36f 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -482,7 +482,13 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) DRM_DEBUG_KMS("\n"); + /* + * The BIOS may leave the PLL in a wonky state where it doesn't + * lock. It needs to be fully powered down to fix it. + */ + intel_disable_dsi_pll(encoder); intel_enable_dsi_pll(encoder); + intel_dsi_prepare(encoder); /* Panel Enable over CRC PMIC */ diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index 916cc92c1400..978cc2668a3d 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -474,14 +474,6 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder) DRM_DEBUG_KMS("\n"); - val = I915_READ(BXT_DSI_PLL_ENABLE); - - if (val & BXT_DSI_PLL_DO_ENABLE) { - WARN(1, "DSI PLL already enabled. Disabling it.\n"); - val &= ~BXT_DSI_PLL_DO_ENABLE; - I915_WRITE(BXT_DSI_PLL_ENABLE, val); - } - /* Configure PLL vales */ if (!bxt_configure_dsi_pll(encoder)) { DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");