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[6/6] drm/i915: Use coarse grained residency counter with byt

Message ID 1489592584-10422-6-git-send-email-mika.kuoppala@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kuoppala March 15, 2017, 3:43 p.m. UTC
Set byt rc residency counters high level as chv does by
default. We lose some accuracy on byt but we can do the calculation
without extra hw read on both platforms, as now they behave
identically in this respect.

v2: use ktime

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 9 ++-------
 drivers/gpu/drm/i915/intel_pm.c | 9 +++------
 2 files changed, 5 insertions(+), 13 deletions(-)

Comments

Chris Wilson March 15, 2017, 3:56 p.m. UTC | #1
On Wed, Mar 15, 2017 at 05:43:04PM +0200, Mika Kuoppala wrote:
> Set byt rc residency counters high level as chv does by
> default. We lose some accuracy on byt but we can do the calculation
> without extra hw read on both platforms, as now they behave
> identically in this respect.
> 
> v2: use ktime
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 9 ++-------
>  drivers/gpu/drm/i915/intel_pm.c | 9 +++------
>  2 files changed, 5 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f73d8db..7fb35a5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1100,11 +1100,6 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
>  	if (prev->ktime) {
>  		u64 time, c0;
>  		u32 render, media;
> -		unsigned int mul;
> -
> -		mul = 1000 * 100; /* scale to threshold% */
> -		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
> -			mul <<= 8;
>  
>  		time = ktime_us_delta(now.ktime, prev->ktime);
>  		time *= dev_priv->czclk_freq;
> @@ -1116,8 +1111,8 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
>  		 */
>  		render = now.render_c0 - prev->render_c0;
>  		media = now.media_c0 - prev->media_c0;
> -		c0 = max(render, media);
> -		c0 *= mul;
> +		c0 = max_t(u64, render, media) << 8; /* upper part of 40 bit */

Keep the comparison at u32, do the promotion afterwards, be kind to
32bit machines, i.e.  c0 *= 1000 * 100 << 8; as before

With that
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f73d8db..7fb35a5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1100,11 +1100,6 @@  static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 	if (prev->ktime) {
 		u64 time, c0;
 		u32 render, media;
-		unsigned int mul;
-
-		mul = 1000 * 100; /* scale to threshold% */
-		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
-			mul <<= 8;
 
 		time = ktime_us_delta(now.ktime, prev->ktime);
 		time *= dev_priv->czclk_freq;
@@ -1116,8 +1111,8 @@  static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 		 */
 		render = now.render_c0 - prev->render_c0;
 		media = now.media_c0 - prev->media_c0;
-		c0 = max(render, media);
-		c0 *= mul;
+		c0 = max_t(u64, render, media) << 8; /* upper part of 40 bit */
+		c0 *= 1000 * 100; /* to usecs and scale to threshold% */
 
 		if (c0 > time * dev_priv->rps.up_threshold)
 			events = GEN6_PM_RP_UP_THRESHOLD;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 19fd11b..41d85ce 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6392,7 +6392,8 @@  static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
 
 	/* allows RC6 residency counter to work */
 	I915_WRITE(VLV_COUNTER_CONTROL,
-		   _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
+		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+				      VLV_MEDIA_RC0_COUNT_EN |
 				      VLV_RENDER_RC0_COUNT_EN |
 				      VLV_MEDIA_RC6_COUNT_EN |
 				      VLV_RENDER_RC6_COUNT_EN));
@@ -8361,7 +8362,7 @@  static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
 	spin_lock_irq(&dev_priv->uncore.lock);
 	saved_ctl = I915_READ_FW(VLV_COUNTER_CONTROL);
 
-	if (!(saved_ctl & VLV_COUNT_RANGE_HIGH))
+	if (WARN_ON(!(saved_ctl & VLV_COUNT_RANGE_HIGH)))
 		I915_WRITE_FW(VLV_COUNTER_CONTROL,
 			      _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
 
@@ -8382,10 +8383,6 @@  static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
 		upper = I915_READ_FW(reg);
 	} while (upper != tmp);
 
-	if (!(saved_ctl & VLV_COUNT_RANGE_HIGH))
-		I915_WRITE_FW(VLV_COUNTER_CONTROL,
-			      _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
-
 	spin_unlock_irq(&dev_priv->uncore.lock);
 
 	return lower | (u64)upper << 8;