| Message ID | 20161102175051.29163-5-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 02/11/2016 17:50, Chris Wilson wrote: > The start of the scheduler, add a hook into request submission for the > scheduler to see the arrival of new requests and prepare its runqueues. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/i915_drv.c | 4 ++++ > drivers/gpu/drm/i915/i915_gem_request.c | 13 +++++++++++++ > drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++ > drivers/gpu/drm/i915/intel_ringbuffer.h | 9 +++++++++ > include/uapi/drm/i915_drm.h | 5 +++++ > 5 files changed, 34 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 79cea49183b3..5a0e885e6104 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -323,6 +323,10 @@ static int i915_getparam(struct drm_device *dev, void *data, > */ > value = i915_gem_mmap_gtt_version(); > break; > + case I915_PARAM_HAS_SCHEDULER: > + value = dev_priv->engine[RCS] && > + dev_priv->engine[RCS]->schedule; > + break; > case I915_PARAM_MMAP_VERSION: > /* Remember to bump this if the version changes! */ > case I915_PARAM_HAS_GEM: > diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c > index 05544dec5de9..9c8605c834f9 100644 > --- a/drivers/gpu/drm/i915/i915_gem_request.c > +++ b/drivers/gpu/drm/i915/i915_gem_request.c > @@ -759,6 +759,19 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) > > i915_gem_mark_busy(engine); > > + /* Let the backend know a new request has arrived that may need > + * to adjust the existing execution schedule due to a high priority > + * request - i.e. we may want to preempt the current request in order > + * to run a high priority dependency chain *before* we can execute this > + * request. > + * > + * This is called before the request is ready to run so that we can > + * decide whether to preempt the entire chain so that it is ready to > + * run at the earliest possible convenience. > + */ > + if (engine->schedule) > + engine->schedule(request, 0); > + > local_bh_disable(); > i915_sw_fence_commit(&request->submit); > local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index 298f0f95dd3f..c9171a058478 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -102,6 +102,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv, > engine->mmio_base = info->mmio_base; > engine->irq_shift = info->irq_shift; > > + /* Nothing to do here, execute in order of dependencies */ > + engine->schedule = NULL; > + > dev_priv->engine[id] = engine; > return 0; > } > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index 062bc8e1872a..75991a3c694b 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -267,6 +267,15 @@ struct intel_engine_cs { > */ > void (*submit_request)(struct drm_i915_gem_request *req); > > + /* Call when the priority on a request has changed and it and its > + * dependencies may need rescheduling. Note the request itself may > + * not be ready to run! > + * > + * Called under the struct_mutex. > + */ > + void (*schedule)(struct drm_i915_gem_request *request, > + int priority); > + > /* Some chipsets are not quite as coherent as advertised and need > * an expensive kick to force a true read of the up-to-date seqno. > * However, the up-to-date seqno is not always required and the last > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index 03725fe89859..1c12a350eca3 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -389,6 +389,11 @@ typedef struct drm_i915_irq_wait { > #define I915_PARAM_MIN_EU_IN_POOL 39 > #define I915_PARAM_MMAP_GTT_VERSION 40 > > +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution > + * priorities and the driver will attempt to execute batches in priority order. > + */ > +#define I915_PARAM_HAS_SCHEDULER 41 > + > typedef struct drm_i915_getparam { > __s32 param; > /* > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 79cea49183b3..5a0e885e6104 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -323,6 +323,10 @@ static int i915_getparam(struct drm_device *dev, void *data, */ value = i915_gem_mmap_gtt_version(); break; + case I915_PARAM_HAS_SCHEDULER: + value = dev_priv->engine[RCS] && + dev_priv->engine[RCS]->schedule; + break; case I915_PARAM_MMAP_VERSION: /* Remember to bump this if the version changes! */ case I915_PARAM_HAS_GEM: diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 05544dec5de9..9c8605c834f9 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -759,6 +759,19 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) i915_gem_mark_busy(engine); + /* Let the backend know a new request has arrived that may need + * to adjust the existing execution schedule due to a high priority + * request - i.e. we may want to preempt the current request in order + * to run a high priority dependency chain *before* we can execute this + * request. + * + * This is called before the request is ready to run so that we can + * decide whether to preempt the entire chain so that it is ready to + * run at the earliest possible convenience. + */ + if (engine->schedule) + engine->schedule(request, 0); + local_bh_disable(); i915_sw_fence_commit(&request->submit); local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 298f0f95dd3f..c9171a058478 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -102,6 +102,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv, engine->mmio_base = info->mmio_base; engine->irq_shift = info->irq_shift; + /* Nothing to do here, execute in order of dependencies */ + engine->schedule = NULL; + dev_priv->engine[id] = engine; return 0; } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 062bc8e1872a..75991a3c694b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -267,6 +267,15 @@ struct intel_engine_cs { */ void (*submit_request)(struct drm_i915_gem_request *req); + /* Call when the priority on a request has changed and it and its + * dependencies may need rescheduling. Note the request itself may + * not be ready to run! + * + * Called under the struct_mutex. + */ + void (*schedule)(struct drm_i915_gem_request *request, + int priority); + /* Some chipsets are not quite as coherent as advertised and need * an expensive kick to force a true read of the up-to-date seqno. * However, the up-to-date seqno is not always required and the last diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 03725fe89859..1c12a350eca3 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -389,6 +389,11 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_MIN_EU_IN_POOL 39 #define I915_PARAM_MMAP_GTT_VERSION 40 +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution + * priorities and the driver will attempt to execute batches in priority order. + */ +#define I915_PARAM_HAS_SCHEDULER 41 + typedef struct drm_i915_getparam { __s32 param; /*
The start of the scheduler, add a hook into request submission for the scheduler to see the arrival of new requests and prepare its runqueues. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_drv.c | 4 ++++ drivers/gpu/drm/i915/i915_gem_request.c | 13 +++++++++++++ drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++ drivers/gpu/drm/i915/intel_ringbuffer.h | 9 +++++++++ include/uapi/drm/i915_drm.h | 5 +++++ 5 files changed, 34 insertions(+)