| Message ID | 20171208220646.4141-1-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Dec 08, 2017 at 10:06:46PM +0000, Lucas De Marchi wrote: > This copies include/drm/i915_pciids.h from kernel as of drm-tip: > drm-tip: 2017y-12m-08d-21h-06m-35s UTC + patch adding INTEL_CFL_IDS that > was missing there[1]. Since this tip name is not easily found maybe it would be good to mention latest kernel commit that touched this file. > The goal is to keep track of the PCI IDs in a > single place (kernel). good idea. > > Right now a simple copy is done to catch up with latest changes there, > although in future it could be more sofisticated pointing the build > system to the external header. Yeap, a real single place would be awesome. > > [1] https://patchwork.freedesktop.org/patch/192410/ > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> For the content itself: (with or without modification on commit message) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > lib/i915_pciids.h | 178 ++++++++++++++++++++++++++++++++++-------------------- > 1 file changed, 111 insertions(+), 67 deletions(-) > > diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h > index 8d6c7270..c65e4489 100644 > --- a/lib/i915_pciids.h > +++ b/lib/i915_pciids.h > @@ -118,92 +118,125 @@ > #define INTEL_IRONLAKE_M_IDS(info) \ > INTEL_VGA_DEVICE(0x0046, info) > > -#define INTEL_SNB_D_IDS(info) \ > +#define INTEL_SNB_D_GT1_IDS(info) \ > INTEL_VGA_DEVICE(0x0102, info), \ > - INTEL_VGA_DEVICE(0x0112, info), \ > - INTEL_VGA_DEVICE(0x0122, info), \ > INTEL_VGA_DEVICE(0x010A, info) > > -#define INTEL_SNB_M_IDS(info) \ > - INTEL_VGA_DEVICE(0x0106, info), \ > +#define INTEL_SNB_D_GT2_IDS(info) \ > + INTEL_VGA_DEVICE(0x0112, info), \ > + INTEL_VGA_DEVICE(0x0122, info) > + > +#define INTEL_SNB_D_IDS(info) \ > + INTEL_SNB_D_GT1_IDS(info), \ > + INTEL_SNB_D_GT2_IDS(info) > + > +#define INTEL_SNB_M_GT1_IDS(info) \ > + INTEL_VGA_DEVICE(0x0106, info) > + > +#define INTEL_SNB_M_GT2_IDS(info) \ > INTEL_VGA_DEVICE(0x0116, info), \ > INTEL_VGA_DEVICE(0x0126, info) > > +#define INTEL_SNB_M_IDS(info) \ > + INTEL_SNB_M_GT1_IDS(info), \ > + INTEL_SNB_M_GT2_IDS(info) > + > +#define INTEL_IVB_M_GT1_IDS(info) \ > + INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */ > + > +#define INTEL_IVB_M_GT2_IDS(info) \ > + INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ > + > #define INTEL_IVB_M_IDS(info) \ > - INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \ > - INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ > + INTEL_IVB_M_GT1_IDS(info), \ > + INTEL_IVB_M_GT2_IDS(info) > > -#define INTEL_IVB_D_IDS(info) \ > +#define INTEL_IVB_D_GT1_IDS(info) \ > INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ > + INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */ > + > +#define INTEL_IVB_D_GT2_IDS(info) \ > INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ > - INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \ > INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ > > +#define INTEL_IVB_D_IDS(info) \ > + INTEL_IVB_D_GT1_IDS(info), \ > + INTEL_IVB_D_GT2_IDS(info) > + > #define INTEL_IVB_Q_IDS(info) \ > INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ > > -#define INTEL_HSW_IDS(info) \ > +#define INTEL_HSW_GT1_IDS(info) \ > INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ > - INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ > - INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ > INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ > - INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ > - INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ > INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ > - INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ > - INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ > INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ > - INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ > - INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ > INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ > - INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ > - INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ > INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ > - INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ > - INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ > INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ > - INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ > - INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ > INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ > - INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ > - INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ > INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ > - INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ > - INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ > INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ > - INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ > - INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ > INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ > - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ > - INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ > INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ > - INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ > - INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ > INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ > - INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ > - INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ > INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ > - INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ > - INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ > INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ > - INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ > - INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ > INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ > + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ > + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ > + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ > + INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */ > + > +#define INTEL_HSW_GT2_IDS(info) \ > + INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ > + INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ > + INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ > + INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ > + INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ > + INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ > + INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ > + INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ > + INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ > + INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ > + INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ > + INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ > + INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ > + INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ > + INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ > INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ > INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ > - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ > INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ > - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ > - INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ > INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ > - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ > - INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ > INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ > + INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */ > + > +#define INTEL_HSW_GT3_IDS(info) \ > + INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ > + INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ > + INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ > + INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ > + INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ > + INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ > + INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ > + INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ > + INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ > + INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ > + INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ > + INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ > + INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ > + INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ > + INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ > + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ > + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ > INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ > - INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ > - INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ > INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ > > +#define INTEL_HSW_IDS(info) \ > + INTEL_HSW_GT1_IDS(info), \ > + INTEL_HSW_GT2_IDS(info), \ > + INTEL_HSW_GT3_IDS(info) > + > #define INTEL_VLV_IDS(info) \ > INTEL_VGA_DEVICE(0x0f30, info), \ > INTEL_VGA_DEVICE(0x0f31, info), \ > @@ -212,17 +245,19 @@ > INTEL_VGA_DEVICE(0x0157, info), \ > INTEL_VGA_DEVICE(0x0155, info) > > -#define INTEL_BDW_GT12_IDS(info) \ > +#define INTEL_BDW_GT1_IDS(info) \ > INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ > INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ > INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ > INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ > - INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ > + INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ > + INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */ > + > +#define INTEL_BDW_GT2_IDS(info) \ > + INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ > INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ > INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ > - INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ > - INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ > - INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \ > + INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ > INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ > INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ > > @@ -243,7 +278,8 @@ > INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ > > #define INTEL_BDW_IDS(info) \ > - INTEL_BDW_GT12_IDS(info), \ > + INTEL_BDW_GT1_IDS(info), \ > + INTEL_BDW_GT2_IDS(info), \ > INTEL_BDW_GT3_IDS(info), \ > INTEL_BDW_RSVD_IDS(info) > > @@ -312,7 +348,7 @@ > > #define INTEL_KBL_GT2_IDS(info) \ > INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ > - INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ > + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ > INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ > INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ > INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ > @@ -334,36 +370,44 @@ > INTEL_KBL_GT3_IDS(info), \ > INTEL_KBL_GT4_IDS(info) > > -#define INTEL_CFL_S_IDS(info) \ > +/* CFL S */ > +#define INTEL_CFL_S_GT1_IDS(info) \ > INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \ > - INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \ > + INTEL_VGA_DEVICE(0x3E93, info) /* SRV GT1 */ > + > +#define INTEL_CFL_S_GT2_IDS(info) \ > INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \ > INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \ > - INTEL_VGA_DEVICE(0x3E96, info) /* SRV GT2 */ > + INTEL_VGA_DEVICE(0x3E96, info) /* SRV GT2 */ > > -#define INTEL_CFL_H_IDS(info) \ > +/* CFL H */ > +#define INTEL_CFL_H_GT2_IDS(info) \ > INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ > - INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ > + INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ > > -#define INTEL_CFL_U_IDS(info) \ > - INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \ > +/* CFL U */ > +#define INTEL_CFL_U_GT3_IDS(info) \ > INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \ > INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ > - INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */ > + INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \ > + INTEL_VGA_DEVICE(0x3EA5, info) /* ULT GT3 */ > > #define INTEL_CFL_IDS(info) \ > - INTEL_CFL_S_IDS(info), \ > - INTEL_CFL_H_IDS(info), \ > - INTEL_CFL_U_IDS(info) > + INTEL_CFL_S_GT1_IDS(info), \ > + INTEL_CFL_S_GT2_IDS(info), \ > + INTEL_CFL_H_GT2_IDS(info), \ > + INTEL_CFL_U_GT3_IDS(info) > > +/* CNL U 2+2 */ > #define INTEL_CNL_U_GT2_IDS(info) \ > - INTEL_VGA_DEVICE(0x5A52, info), \ > + INTEL_VGA_DEVICE(0x5A52, info), \ > INTEL_VGA_DEVICE(0x5A5A, info), \ > INTEL_VGA_DEVICE(0x5A42, info), \ > INTEL_VGA_DEVICE(0x5A4A, info) > > +/* CNL Y 2+2 */ > #define INTEL_CNL_Y_GT2_IDS(info) \ > - INTEL_VGA_DEVICE(0x5A51, info), \ > + INTEL_VGA_DEVICE(0x5A51, info), \ > INTEL_VGA_DEVICE(0x5A59, info), \ > INTEL_VGA_DEVICE(0x5A41, info), \ > INTEL_VGA_DEVICE(0x5A49, info), \ > -- > 2.14.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Rodrigo Vivi (2017-12-19 21:59:43) > On Fri, Dec 08, 2017 at 10:06:46PM +0000, Lucas De Marchi wrote: > > This copies include/drm/i915_pciids.h from kernel as of drm-tip: > > drm-tip: 2017y-12m-08d-21h-06m-35s UTC + patch adding INTEL_CFL_IDS that > > was missing there[1]. > > Since this tip name is not easily found maybe it would be good to > mention latest kernel commit that touched this file. > > > The goal is to keep track of the PCI IDs in a > > single place (kernel). > > good idea. > > > > > Right now a simple copy is done to catch up with latest changes there, > > although in future it could be more sofisticated pointing the build > > system to the external header. > > Yeap, a real single place would be awesome. Whilst maintaining independence of the igt build itself? -Chris
On Tue, Dec 19, 2017 at 10:07:30PM +0000, Chris Wilson wrote: > Quoting Rodrigo Vivi (2017-12-19 21:59:43) > > On Fri, Dec 08, 2017 at 10:06:46PM +0000, Lucas De Marchi wrote: > > > This copies include/drm/i915_pciids.h from kernel as of drm-tip: > > > drm-tip: 2017y-12m-08d-21h-06m-35s UTC + patch adding INTEL_CFL_IDS that > > > was missing there[1]. > > > > Since this tip name is not easily found maybe it would be good to > > mention latest kernel commit that touched this file. > > > > > The goal is to keep track of the PCI IDs in a > > > single place (kernel). > > > > good idea. > > > > > > > > Right now a simple copy is done to catch up with latest changes there, > > > although in future it could be more sofisticated pointing the build > > > system to the external header. > > > > Yeap, a real single place would be awesome. > > Whilst maintaining independence of the igt build itself? yeap... nevermind... I was just in another discussion about detection of cnl on vaapi driver and I realized that the userspace individual detection has its advantages... > -Chris
On Tue, 2017-12-19 at 15:28 -0800, Rodrigo Vivi wrote: > On Tue, Dec 19, 2017 at 10:07:30PM +0000, Chris Wilson wrote: > > Quoting Rodrigo Vivi (2017-12-19 21:59:43) > > > On Fri, Dec 08, 2017 at 10:06:46PM +0000, Lucas De Marchi wrote: > > > > This copies include/drm/i915_pciids.h from kernel as of drm-tip: > > > > drm-tip: 2017y-12m-08d-21h-06m-35s UTC + patch adding INTEL_CFL_IDS > > > > that > > > > was missing there[1]. > > > > > > Since this tip name is not easily found maybe it would be good to > > > mention latest kernel commit that touched this file. > > > > > > > The goal is to keep track of the PCI IDs in a > > > > single place (kernel). > > > > > > good idea. > > > > > > > > > > > Right now a simple copy is done to catch up with latest changes there, > > > > although in future it could be more sofisticated pointing the build > > > > system to the external header. > > > > > > Yeap, a real single place would be awesome. > > > > Whilst maintaining independence of the igt build itself? > > yeap... nevermind... > I was just in another discussion about detection of cnl on vaapi driver > and I realized that the userspace individual detection has its advantages... I get the benefit of not tying i-g-t to particular kernel versions, but we may need to think in a way to alleviate the tedious work of updating the IDs across the projects. Some alternatives: 1) Move header to e.g. include/external/i915_pciids.h and add a scripts/i915-update-ids that receives the kernel directory as argument. The script does whateve is needed to update the header, which may or may not include adding a verbiage on top of the header /* This header is automatically generated, do not edit it */ 2) Just create a policy that changes to this header needs to actually be a copy from the kernel header with the commit hash in the commit message 3) A mix or partial implementation of (1) and (2). What do you think? Lucas De Marchi
Quoting De Marchi, Lucas (2017-12-20 20:06:24) > On Tue, 2017-12-19 at 15:28 -0800, Rodrigo Vivi wrote: > > On Tue, Dec 19, 2017 at 10:07:30PM +0000, Chris Wilson wrote: > > > Quoting Rodrigo Vivi (2017-12-19 21:59:43) > > > > On Fri, Dec 08, 2017 at 10:06:46PM +0000, Lucas De Marchi wrote: > > > > > This copies include/drm/i915_pciids.h from kernel as of drm-tip: > > > > > drm-tip: 2017y-12m-08d-21h-06m-35s UTC + patch adding INTEL_CFL_IDS > > > > > that > > > > > was missing there[1]. > > > > > > > > Since this tip name is not easily found maybe it would be good to > > > > mention latest kernel commit that touched this file. > > > > > > > > > The goal is to keep track of the PCI IDs in a > > > > > single place (kernel). > > > > > > > > good idea. > > > > > > > > > > > > > > Right now a simple copy is done to catch up with latest changes there, > > > > > although in future it could be more sofisticated pointing the build > > > > > system to the external header. > > > > > > > > Yeap, a real single place would be awesome. > > > > > > Whilst maintaining independence of the igt build itself? > > > > yeap... nevermind... > > I was just in another discussion about detection of cnl on vaapi driver > > and I realized that the userspace individual detection has its advantages... > > I get the benefit of not tying i-g-t to particular kernel versions, but we may > need to think in a way to alleviate the tedious work of updating the IDs > across the projects. We did that, it's called i915_pciids.h. We said we would put all the ids into a single header in a format that both userspace and the kernel could digest, then copy it wherever required. It's just a cp; git commit. The difficult part is then tying the pci-id to the internal db of the project, and our proposal to share that was shot down. -Chris
On Tue, 2017-12-19 at 13:59 -0800, Rodrigo Vivi wrote: > On Fri, Dec 08, 2017 at 10:06:46PM +0000, Lucas De Marchi wrote: > > This copies include/drm/i915_pciids.h from kernel as of drm-tip: > > drm-tip: 2017y-12m-08d-21h-06m-35s UTC + patch adding INTEL_CFL_IDS that > > was missing there[1]. > > Since this tip name is not easily found maybe it would be good to > mention latest kernel commit that touched this file. At the time I sent this the additional kernel patch with CFL IDs were not applied yet. I was already expecting to have to change this message, but I forgot to tell here. I will send a v2. thanks Lucas De Marchi
On Wed, Dec 20, 2017 at 08:06:24PM +0000, De Marchi, Lucas wrote: > On Tue, 2017-12-19 at 15:28 -0800, Rodrigo Vivi wrote: > > On Tue, Dec 19, 2017 at 10:07:30PM +0000, Chris Wilson wrote: > > > Quoting Rodrigo Vivi (2017-12-19 21:59:43) > > > > On Fri, Dec 08, 2017 at 10:06:46PM +0000, Lucas De Marchi wrote: > > > > > This copies include/drm/i915_pciids.h from kernel as of drm-tip: > > > > > drm-tip: 2017y-12m-08d-21h-06m-35s UTC + patch adding INTEL_CFL_IDS > > > > > that > > > > > was missing there[1]. > > > > > > > > Since this tip name is not easily found maybe it would be good to > > > > mention latest kernel commit that touched this file. > > > > > > > > > The goal is to keep track of the PCI IDs in a > > > > > single place (kernel). > > > > > > > > good idea. > > > > > > > > > > > > > > Right now a simple copy is done to catch up with latest changes there, > > > > > although in future it could be more sofisticated pointing the build > > > > > system to the external header. > > > > > > > > Yeap, a real single place would be awesome. > > > > > > Whilst maintaining independence of the igt build itself? > > > > yeap... nevermind... > > I was just in another discussion about detection of cnl on vaapi driver > > and I realized that the userspace individual detection has its advantages... > > I get the benefit of not tying i-g-t to particular kernel versions, but we may > need to think in a way to alleviate the tedious work of updating the IDs > across the projects. > > Some alternatives: > > 1) Move header to e.g. include/external/i915_pciids.h and add a > scripts/i915-update-ids that receives the kernel directory as argument. The > script does whateve is needed to update the header, which may or may not > include adding a verbiage on top of the header > > /* This header is automatically generated, do not edit it */ > +1. An igt/tools/<tool> that could use some sort of curl https://cgit.freedesktop.org/drm-tip/tree/include/drm/i915_pciids.h and generate the igt out of it. possibly the libdrm as well? or maybe a git instead the curl so we could get the last commit id touching this file and add to the new auto-generated commit as reference. > 2) Just create a policy that changes to this header needs to actually be a > copy from the kernel header with the commit hash in the commit message > > 3) A mix or partial implementation of (1) and (2). > > What do you think? > > Lucas De Marchi
Hi all, restarting a very old thread since Dmitry is interested in tackle the issue that we have to propagate and keep all IDs in sync across the stack. He has few ideas of i915 ioctls in a way that it wouldn't necessarily tie build dependencies etc.. Since I believe this place is the best one to discuss ideas like that let me invite him for the discussion in a way he can explain his ideas here. Also cc'ing some relevant mailing lists. Thanks, Rodrigo. On Wed, Dec 20, 2017 at 12:06:24PM -0800, De Marchi, Lucas wrote: > On Tue, 2017-12-19 at 15:28 -0800, Rodrigo Vivi wrote: > > On Tue, Dec 19, 2017 at 10:07:30PM +0000, Chris Wilson wrote: > > > Quoting Rodrigo Vivi (2017-12-19 21:59:43) > > > > On Fri, Dec 08, 2017 at 10:06:46PM +0000, Lucas De Marchi wrote: > > > > > This copies include/drm/i915_pciids.h from kernel as of drm-tip: > > > > > drm-tip: 2017y-12m-08d-21h-06m-35s UTC + patch adding INTEL_CFL_IDS > > > > > that > > > > > was missing there[1]. > > > > > > > > Since this tip name is not easily found maybe it would be good to > > > > mention latest kernel commit that touched this file. > > > > > > > > > The goal is to keep track of the PCI IDs in a > > > > > single place (kernel). > > > > > > > > good idea. > > > > > > > > > > > > > > Right now a simple copy is done to catch up with latest changes there, > > > > > although in future it could be more sofisticated pointing the build > > > > > system to the external header. > > > > > > > > Yeap, a real single place would be awesome. > > > > > > Whilst maintaining independence of the igt build itself? > > > > yeap... nevermind... > > I was just in another discussion about detection of cnl on vaapi driver > > and I realized that the userspace individual detection has its advantages... > > I get the benefit of not tying i-g-t to particular kernel versions, but we may > need to think in a way to alleviate the tedious work of updating the IDs > across the projects. > > Some alternatives: > > 1) Move header to e.g. include/external/i915_pciids.h and add a > scripts/i915-update-ids that receives the kernel directory as argument. The > script does whateve is needed to update the header, which may or may not > include adding a verbiage on top of the header > > /* This header is automatically generated, do not edit it */ > > 2) Just create a policy that changes to this header needs to actually be a > copy from the kernel header with the commit hash in the commit message > > 3) A mix or partial implementation of (1) and (2). > > What do you think? > > Lucas De Marchi
diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h index 8d6c7270..c65e4489 100644 --- a/lib/i915_pciids.h +++ b/lib/i915_pciids.h @@ -118,92 +118,125 @@ #define INTEL_IRONLAKE_M_IDS(info) \ INTEL_VGA_DEVICE(0x0046, info) -#define INTEL_SNB_D_IDS(info) \ +#define INTEL_SNB_D_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x0102, info), \ - INTEL_VGA_DEVICE(0x0112, info), \ - INTEL_VGA_DEVICE(0x0122, info), \ INTEL_VGA_DEVICE(0x010A, info) -#define INTEL_SNB_M_IDS(info) \ - INTEL_VGA_DEVICE(0x0106, info), \ +#define INTEL_SNB_D_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x0112, info), \ + INTEL_VGA_DEVICE(0x0122, info) + +#define INTEL_SNB_D_IDS(info) \ + INTEL_SNB_D_GT1_IDS(info), \ + INTEL_SNB_D_GT2_IDS(info) + +#define INTEL_SNB_M_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x0106, info) + +#define INTEL_SNB_M_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x0116, info), \ INTEL_VGA_DEVICE(0x0126, info) +#define INTEL_SNB_M_IDS(info) \ + INTEL_SNB_M_GT1_IDS(info), \ + INTEL_SNB_M_GT2_IDS(info) + +#define INTEL_IVB_M_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */ + +#define INTEL_IVB_M_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ + #define INTEL_IVB_M_IDS(info) \ - INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \ - INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ + INTEL_IVB_M_GT1_IDS(info), \ + INTEL_IVB_M_GT2_IDS(info) -#define INTEL_IVB_D_IDS(info) \ +#define INTEL_IVB_D_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ + INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */ + +#define INTEL_IVB_D_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ - INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \ INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ +#define INTEL_IVB_D_IDS(info) \ + INTEL_IVB_D_GT1_IDS(info), \ + INTEL_IVB_D_GT2_IDS(info) + #define INTEL_IVB_Q_IDS(info) \ INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ -#define INTEL_HSW_IDS(info) \ +#define INTEL_HSW_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ - INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ - INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ - INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ - INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ - INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ - INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ - INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ - INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ - INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ - INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ - INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ - INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ - INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ - INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ - INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ - INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ - INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ - INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ - INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ - INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */ + +#define INTEL_HSW_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ + INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ + INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ + INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ + INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ + INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ + INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ - INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ - INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */ + +#define INTEL_HSW_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ + INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ + INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ + INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ + INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ + INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ + INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ - INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ +#define INTEL_HSW_IDS(info) \ + INTEL_HSW_GT1_IDS(info), \ + INTEL_HSW_GT2_IDS(info), \ + INTEL_HSW_GT3_IDS(info) + #define INTEL_VLV_IDS(info) \ INTEL_VGA_DEVICE(0x0f30, info), \ INTEL_VGA_DEVICE(0x0f31, info), \ @@ -212,17 +245,19 @@ INTEL_VGA_DEVICE(0x0157, info), \ INTEL_VGA_DEVICE(0x0155, info) -#define INTEL_BDW_GT12_IDS(info) \ +#define INTEL_BDW_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ - INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ + INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ + INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */ + +#define INTEL_BDW_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ - INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ - INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ - INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \ + INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ @@ -243,7 +278,8 @@ INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ #define INTEL_BDW_IDS(info) \ - INTEL_BDW_GT12_IDS(info), \ + INTEL_BDW_GT1_IDS(info), \ + INTEL_BDW_GT2_IDS(info), \ INTEL_BDW_GT3_IDS(info), \ INTEL_BDW_RSVD_IDS(info) @@ -312,7 +348,7 @@ #define INTEL_KBL_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ - INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ @@ -334,36 +370,44 @@ INTEL_KBL_GT3_IDS(info), \ INTEL_KBL_GT4_IDS(info) -#define INTEL_CFL_S_IDS(info) \ +/* CFL S */ +#define INTEL_CFL_S_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \ - INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \ + INTEL_VGA_DEVICE(0x3E93, info) /* SRV GT1 */ + +#define INTEL_CFL_S_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \ INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \ - INTEL_VGA_DEVICE(0x3E96, info) /* SRV GT2 */ + INTEL_VGA_DEVICE(0x3E96, info) /* SRV GT2 */ -#define INTEL_CFL_H_IDS(info) \ +/* CFL H */ +#define INTEL_CFL_H_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ - INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ + INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ -#define INTEL_CFL_U_IDS(info) \ - INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \ +/* CFL U */ +#define INTEL_CFL_U_GT3_IDS(info) \ INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */ + INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x3EA5, info) /* ULT GT3 */ #define INTEL_CFL_IDS(info) \ - INTEL_CFL_S_IDS(info), \ - INTEL_CFL_H_IDS(info), \ - INTEL_CFL_U_IDS(info) + INTEL_CFL_S_GT1_IDS(info), \ + INTEL_CFL_S_GT2_IDS(info), \ + INTEL_CFL_H_GT2_IDS(info), \ + INTEL_CFL_U_GT3_IDS(info) +/* CNL U 2+2 */ #define INTEL_CNL_U_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x5A52, info), \ + INTEL_VGA_DEVICE(0x5A52, info), \ INTEL_VGA_DEVICE(0x5A5A, info), \ INTEL_VGA_DEVICE(0x5A42, info), \ INTEL_VGA_DEVICE(0x5A4A, info) +/* CNL Y 2+2 */ #define INTEL_CNL_Y_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x5A51, info), \ + INTEL_VGA_DEVICE(0x5A51, info), \ INTEL_VGA_DEVICE(0x5A59, info), \ INTEL_VGA_DEVICE(0x5A41, info), \ INTEL_VGA_DEVICE(0x5A49, info), \
This copies include/drm/i915_pciids.h from kernel as of drm-tip: drm-tip: 2017y-12m-08d-21h-06m-35s UTC + patch adding INTEL_CFL_IDS that was missing there[1]. The goal is to keep track of the PCI IDs in a single place (kernel). Right now a simple copy is done to catch up with latest changes there, although in future it could be more sofisticated pointing the build system to the external header. [1] https://patchwork.freedesktop.org/patch/192410/ Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- lib/i915_pciids.h | 178 ++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 111 insertions(+), 67 deletions(-)