| Message ID | 20190213144536.21661-2-David.Francis@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Make DRM DSC helpers more generally usable | expand |
On 2019-02-13 9:45 a.m., David Francis wrote: > The function intel_compute_rc_parameters is part of the dsc spec > and is not driver-specific. Other drm drivers might like to use > it. The function is not changed; just moved and renamed. > > Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> This one also needs an RB or AB from i915 guys. Harry > --- > drivers/gpu/drm/drm_dsc.c | 133 ++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_vdsc.c | 125 +--------------------------- > include/drm/drm_dsc.h | 1 + > 3 files changed, 135 insertions(+), 124 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c > index bc2b23adb072..4b0e3c9c3ff8 100644 > --- a/drivers/gpu/drm/drm_dsc.c > +++ b/drivers/gpu/drm/drm_dsc.c > @@ -11,6 +11,7 @@ > #include <linux/init.h> > #include <linux/errno.h> > #include <linux/byteorder/generic.h> > +#include <drm/drm_print.h> > #include <drm/drm_dp_helper.h> > #include <drm/drm_dsc.h> > > @@ -226,3 +227,135 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, > /* PPS 94 - 127 are O */ > } > EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack); > + > +/** > + * drm_dsc_compute_rc_parameters() - Write rate control > + * parameters to the dsc configuration. Some configuration > + * fields must be present beforehand. > + * > + * @dsc_cfg: > + * DSC Configuration data partially filled by driver > + */ > +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) > +{ > + unsigned long groups_per_line = 0; > + unsigned long groups_total = 0; > + unsigned long num_extra_mux_bits = 0; > + unsigned long slice_bits = 0; > + unsigned long hrd_delay = 0; > + unsigned long final_scale = 0; > + unsigned long rbs_min = 0; > + > + /* Number of groups used to code each line of a slice */ > + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, > + DSC_RC_PIXELS_PER_GROUP); > + > + /* chunksize in Bytes */ > + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * > + vdsc_cfg->bits_per_pixel, > + (8 * 16)); > + > + if (vdsc_cfg->convert_rgb) > + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + > + (4 * vdsc_cfg->bits_per_component + 4) > + - 2); > + else > + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + > + (4 * vdsc_cfg->bits_per_component + 4) + > + 2 * (4 * vdsc_cfg->bits_per_component) - 2; > + /* Number of bits in one Slice */ > + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; > + > + while ((num_extra_mux_bits > 0) && > + ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) > + num_extra_mux_bits--; > + > + if (groups_per_line < vdsc_cfg->initial_scale_value - 8) > + vdsc_cfg->initial_scale_value = groups_per_line + 8; > + > + /* scale_decrement_interval calculation according to DSC spec 1.11 */ > + if (vdsc_cfg->initial_scale_value > 8) > + vdsc_cfg->scale_decrement_interval = groups_per_line / > + (vdsc_cfg->initial_scale_value - 8); > + else > + vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; > + > + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - > + (vdsc_cfg->initial_xmit_delay * > + vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; > + > + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { > + DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); > + return -ERANGE; > + } > + > + final_scale = (vdsc_cfg->rc_model_size * 8) / > + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); > + if (vdsc_cfg->slice_height > 1) > + /* > + * NflBpgOffset is 16 bit value with 11 fractional bits > + * hence we multiply by 2^11 for preserving the > + * fractional part > + */ > + vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), > + (vdsc_cfg->slice_height - 1)); > + else > + vdsc_cfg->nfl_bpg_offset = 0; > + > + /* 2^16 - 1 */ > + if (vdsc_cfg->nfl_bpg_offset > 65535) { > + DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n"); > + return -ERANGE; > + } > + > + /* Number of groups used to code the entire slice */ > + groups_total = groups_per_line * vdsc_cfg->slice_height; > + > + /* slice_bpg_offset is 16 bit value with 11 fractional bits */ > + vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - > + vdsc_cfg->initial_offset + > + num_extra_mux_bits) << 11), > + groups_total); > + > + if (final_scale > 9) { > + /* > + * ScaleIncrementInterval = > + * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) > + * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, > + * we need divide by 2^11 from pstDscCfg values > + */ > + vdsc_cfg->scale_increment_interval = > + (vdsc_cfg->final_offset * (1 << 11)) / > + ((vdsc_cfg->nfl_bpg_offset + > + vdsc_cfg->slice_bpg_offset) * > + (final_scale - 9)); > + } else { > + /* > + * If finalScaleValue is less than or equal to 9, a value of 0 should > + * be used to disable the scale increment at the end of the slice > + */ > + vdsc_cfg->scale_increment_interval = 0; > + } > + > + if (vdsc_cfg->scale_increment_interval > 65535) { > + DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n"); > + return -ERANGE; > + } > + > + /* > + * DSC spec mentions that bits_per_pixel specifies the target > + * bits/pixel (bpp) rate that is used by the encoder, > + * in steps of 1/16 of a bit per pixel > + */ > + rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + > + DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * > + vdsc_cfg->bits_per_pixel, 16) + > + groups_per_line * vdsc_cfg->first_line_bpg_offset; > + > + hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); > + vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; > + vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; > + > + return 0; > +} > +EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c > index c56ba0e04044..c76cec8bfb74 100644 > --- a/drivers/gpu/drm/i915/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/intel_vdsc.c > @@ -318,129 +318,6 @@ static int get_column_index_for_rc_params(u8 bits_per_component) > } > } > > -static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) > -{ > - unsigned long groups_per_line = 0; > - unsigned long groups_total = 0; > - unsigned long num_extra_mux_bits = 0; > - unsigned long slice_bits = 0; > - unsigned long hrd_delay = 0; > - unsigned long final_scale = 0; > - unsigned long rbs_min = 0; > - > - /* Number of groups used to code each line of a slice */ > - groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, > - DSC_RC_PIXELS_PER_GROUP); > - > - /* chunksize in Bytes */ > - vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * > - vdsc_cfg->bits_per_pixel, > - (8 * 16)); > - > - if (vdsc_cfg->convert_rgb) > - num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + > - (4 * vdsc_cfg->bits_per_component + 4) > - - 2); > - else > - num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + > - (4 * vdsc_cfg->bits_per_component + 4) + > - 2 * (4 * vdsc_cfg->bits_per_component) - 2; > - /* Number of bits in one Slice */ > - slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; > - > - while ((num_extra_mux_bits > 0) && > - ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) > - num_extra_mux_bits--; > - > - if (groups_per_line < vdsc_cfg->initial_scale_value - 8) > - vdsc_cfg->initial_scale_value = groups_per_line + 8; > - > - /* scale_decrement_interval calculation according to DSC spec 1.11 */ > - if (vdsc_cfg->initial_scale_value > 8) > - vdsc_cfg->scale_decrement_interval = groups_per_line / > - (vdsc_cfg->initial_scale_value - 8); > - else > - vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; > - > - vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - > - (vdsc_cfg->initial_xmit_delay * > - vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; > - > - if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { > - DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); > - return -ERANGE; > - } > - > - final_scale = (vdsc_cfg->rc_model_size * 8) / > - (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); > - if (vdsc_cfg->slice_height > 1) > - /* > - * NflBpgOffset is 16 bit value with 11 fractional bits > - * hence we multiply by 2^11 for preserving the > - * fractional part > - */ > - vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), > - (vdsc_cfg->slice_height - 1)); > - else > - vdsc_cfg->nfl_bpg_offset = 0; > - > - /* 2^16 - 1 */ > - if (vdsc_cfg->nfl_bpg_offset > 65535) { > - DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n"); > - return -ERANGE; > - } > - > - /* Number of groups used to code the entire slice */ > - groups_total = groups_per_line * vdsc_cfg->slice_height; > - > - /* slice_bpg_offset is 16 bit value with 11 fractional bits */ > - vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - > - vdsc_cfg->initial_offset + > - num_extra_mux_bits) << 11), > - groups_total); > - > - if (final_scale > 9) { > - /* > - * ScaleIncrementInterval = > - * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) > - * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, > - * we need divide by 2^11 from pstDscCfg values > - */ > - vdsc_cfg->scale_increment_interval = > - (vdsc_cfg->final_offset * (1 << 11)) / > - ((vdsc_cfg->nfl_bpg_offset + > - vdsc_cfg->slice_bpg_offset) * > - (final_scale - 9)); > - } else { > - /* > - * If finalScaleValue is less than or equal to 9, a value of 0 should > - * be used to disable the scale increment at the end of the slice > - */ > - vdsc_cfg->scale_increment_interval = 0; > - } > - > - if (vdsc_cfg->scale_increment_interval > 65535) { > - DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n"); > - return -ERANGE; > - } > - > - /* > - * DSC spec mentions that bits_per_pixel specifies the target > - * bits/pixel (bpp) rate that is used by the encoder, > - * in steps of 1/16 of a bit per pixel > - */ > - rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + > - DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * > - vdsc_cfg->bits_per_pixel, 16) + > - groups_per_line * vdsc_cfg->first_line_bpg_offset; > - > - hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); > - vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; > - vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; > - > - return 0; > -} > - > int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > struct intel_crtc_state *pipe_config) > { > @@ -575,7 +452,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / > (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); > > - return intel_compute_rc_parameters(vdsc_cfg); > + return drm_dsc_compute_rc_parameters(vdsc_cfg); > } > > enum intel_display_power_domain > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h > index d03f1b83421a..ad43494f1cc8 100644 > --- a/include/drm/drm_dsc.h > +++ b/include/drm/drm_dsc.h > @@ -481,5 +481,6 @@ struct drm_dsc_pps_infoframe { > void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp); > void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, > const struct drm_dsc_config *dsc_cfg); > +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); > > #endif /* _DRM_DSC_H_ */ >
On Wed, Feb 13, 2019 at 09:45:34AM -0500, David Francis wrote: > The function intel_compute_rc_parameters is part of the dsc spec > and is not driver-specific. Other drm drivers might like to use > it. The function is not changed; just moved and renamed. > Yes this sounds fair since its DSC spec related and can move to drm_dsc.c. As a part of this series or later you should also consider moving the rc_parameters struct for input bpc/output BPP combinations to DRM since that is also purely spec related. With this change and compute_rc_params function in DRM, please add appropriate description of the function as part of kernel documentation. With the documentation change, you have my r-b. Regards Manasi > Signed-off-by: David Francis <David.Francis@amd.com> > --- > drivers/gpu/drm/drm_dsc.c | 133 ++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_vdsc.c | 125 +--------------------------- > include/drm/drm_dsc.h | 1 + > 3 files changed, 135 insertions(+), 124 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c > index bc2b23adb072..4b0e3c9c3ff8 100644 > --- a/drivers/gpu/drm/drm_dsc.c > +++ b/drivers/gpu/drm/drm_dsc.c > @@ -11,6 +11,7 @@ > #include <linux/init.h> > #include <linux/errno.h> > #include <linux/byteorder/generic.h> > +#include <drm/drm_print.h> > #include <drm/drm_dp_helper.h> > #include <drm/drm_dsc.h> > > @@ -226,3 +227,135 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, > /* PPS 94 - 127 are O */ > } > EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack); > + > +/** > + * drm_dsc_compute_rc_parameters() - Write rate control > + * parameters to the dsc configuration. Some configuration > + * fields must be present beforehand. > + * > + * @dsc_cfg: > + * DSC Configuration data partially filled by driver > + */ > +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) > +{ > + unsigned long groups_per_line = 0; > + unsigned long groups_total = 0; > + unsigned long num_extra_mux_bits = 0; > + unsigned long slice_bits = 0; > + unsigned long hrd_delay = 0; > + unsigned long final_scale = 0; > + unsigned long rbs_min = 0; > + > + /* Number of groups used to code each line of a slice */ > + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, > + DSC_RC_PIXELS_PER_GROUP); > + > + /* chunksize in Bytes */ > + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * > + vdsc_cfg->bits_per_pixel, > + (8 * 16)); > + > + if (vdsc_cfg->convert_rgb) > + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + > + (4 * vdsc_cfg->bits_per_component + 4) > + - 2); > + else > + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + > + (4 * vdsc_cfg->bits_per_component + 4) + > + 2 * (4 * vdsc_cfg->bits_per_component) - 2; > + /* Number of bits in one Slice */ > + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; > + > + while ((num_extra_mux_bits > 0) && > + ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) > + num_extra_mux_bits--; > + > + if (groups_per_line < vdsc_cfg->initial_scale_value - 8) > + vdsc_cfg->initial_scale_value = groups_per_line + 8; > + > + /* scale_decrement_interval calculation according to DSC spec 1.11 */ > + if (vdsc_cfg->initial_scale_value > 8) > + vdsc_cfg->scale_decrement_interval = groups_per_line / > + (vdsc_cfg->initial_scale_value - 8); > + else > + vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; > + > + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - > + (vdsc_cfg->initial_xmit_delay * > + vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; > + > + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { > + DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); > + return -ERANGE; > + } > + > + final_scale = (vdsc_cfg->rc_model_size * 8) / > + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); > + if (vdsc_cfg->slice_height > 1) > + /* > + * NflBpgOffset is 16 bit value with 11 fractional bits > + * hence we multiply by 2^11 for preserving the > + * fractional part > + */ > + vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), > + (vdsc_cfg->slice_height - 1)); > + else > + vdsc_cfg->nfl_bpg_offset = 0; > + > + /* 2^16 - 1 */ > + if (vdsc_cfg->nfl_bpg_offset > 65535) { > + DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n"); > + return -ERANGE; > + } > + > + /* Number of groups used to code the entire slice */ > + groups_total = groups_per_line * vdsc_cfg->slice_height; > + > + /* slice_bpg_offset is 16 bit value with 11 fractional bits */ > + vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - > + vdsc_cfg->initial_offset + > + num_extra_mux_bits) << 11), > + groups_total); > + > + if (final_scale > 9) { > + /* > + * ScaleIncrementInterval = > + * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) > + * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, > + * we need divide by 2^11 from pstDscCfg values > + */ > + vdsc_cfg->scale_increment_interval = > + (vdsc_cfg->final_offset * (1 << 11)) / > + ((vdsc_cfg->nfl_bpg_offset + > + vdsc_cfg->slice_bpg_offset) * > + (final_scale - 9)); > + } else { > + /* > + * If finalScaleValue is less than or equal to 9, a value of 0 should > + * be used to disable the scale increment at the end of the slice > + */ > + vdsc_cfg->scale_increment_interval = 0; > + } > + > + if (vdsc_cfg->scale_increment_interval > 65535) { > + DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n"); > + return -ERANGE; > + } > + > + /* > + * DSC spec mentions that bits_per_pixel specifies the target > + * bits/pixel (bpp) rate that is used by the encoder, > + * in steps of 1/16 of a bit per pixel > + */ > + rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + > + DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * > + vdsc_cfg->bits_per_pixel, 16) + > + groups_per_line * vdsc_cfg->first_line_bpg_offset; > + > + hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); > + vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; > + vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; > + > + return 0; > +} > +EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c > index c56ba0e04044..c76cec8bfb74 100644 > --- a/drivers/gpu/drm/i915/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/intel_vdsc.c > @@ -318,129 +318,6 @@ static int get_column_index_for_rc_params(u8 bits_per_component) > } > } > > -static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) > -{ > - unsigned long groups_per_line = 0; > - unsigned long groups_total = 0; > - unsigned long num_extra_mux_bits = 0; > - unsigned long slice_bits = 0; > - unsigned long hrd_delay = 0; > - unsigned long final_scale = 0; > - unsigned long rbs_min = 0; > - > - /* Number of groups used to code each line of a slice */ > - groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, > - DSC_RC_PIXELS_PER_GROUP); > - > - /* chunksize in Bytes */ > - vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * > - vdsc_cfg->bits_per_pixel, > - (8 * 16)); > - > - if (vdsc_cfg->convert_rgb) > - num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + > - (4 * vdsc_cfg->bits_per_component + 4) > - - 2); > - else > - num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + > - (4 * vdsc_cfg->bits_per_component + 4) + > - 2 * (4 * vdsc_cfg->bits_per_component) - 2; > - /* Number of bits in one Slice */ > - slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; > - > - while ((num_extra_mux_bits > 0) && > - ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) > - num_extra_mux_bits--; > - > - if (groups_per_line < vdsc_cfg->initial_scale_value - 8) > - vdsc_cfg->initial_scale_value = groups_per_line + 8; > - > - /* scale_decrement_interval calculation according to DSC spec 1.11 */ > - if (vdsc_cfg->initial_scale_value > 8) > - vdsc_cfg->scale_decrement_interval = groups_per_line / > - (vdsc_cfg->initial_scale_value - 8); > - else > - vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; > - > - vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - > - (vdsc_cfg->initial_xmit_delay * > - vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; > - > - if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { > - DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); > - return -ERANGE; > - } > - > - final_scale = (vdsc_cfg->rc_model_size * 8) / > - (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); > - if (vdsc_cfg->slice_height > 1) > - /* > - * NflBpgOffset is 16 bit value with 11 fractional bits > - * hence we multiply by 2^11 for preserving the > - * fractional part > - */ > - vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), > - (vdsc_cfg->slice_height - 1)); > - else > - vdsc_cfg->nfl_bpg_offset = 0; > - > - /* 2^16 - 1 */ > - if (vdsc_cfg->nfl_bpg_offset > 65535) { > - DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n"); > - return -ERANGE; > - } > - > - /* Number of groups used to code the entire slice */ > - groups_total = groups_per_line * vdsc_cfg->slice_height; > - > - /* slice_bpg_offset is 16 bit value with 11 fractional bits */ > - vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - > - vdsc_cfg->initial_offset + > - num_extra_mux_bits) << 11), > - groups_total); > - > - if (final_scale > 9) { > - /* > - * ScaleIncrementInterval = > - * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) > - * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, > - * we need divide by 2^11 from pstDscCfg values > - */ > - vdsc_cfg->scale_increment_interval = > - (vdsc_cfg->final_offset * (1 << 11)) / > - ((vdsc_cfg->nfl_bpg_offset + > - vdsc_cfg->slice_bpg_offset) * > - (final_scale - 9)); > - } else { > - /* > - * If finalScaleValue is less than or equal to 9, a value of 0 should > - * be used to disable the scale increment at the end of the slice > - */ > - vdsc_cfg->scale_increment_interval = 0; > - } > - > - if (vdsc_cfg->scale_increment_interval > 65535) { > - DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n"); > - return -ERANGE; > - } > - > - /* > - * DSC spec mentions that bits_per_pixel specifies the target > - * bits/pixel (bpp) rate that is used by the encoder, > - * in steps of 1/16 of a bit per pixel > - */ > - rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + > - DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * > - vdsc_cfg->bits_per_pixel, 16) + > - groups_per_line * vdsc_cfg->first_line_bpg_offset; > - > - hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); > - vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; > - vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; > - > - return 0; > -} > - > int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > struct intel_crtc_state *pipe_config) > { > @@ -575,7 +452,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / > (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); > > - return intel_compute_rc_parameters(vdsc_cfg); > + return drm_dsc_compute_rc_parameters(vdsc_cfg); > } > > enum intel_display_power_domain > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h > index d03f1b83421a..ad43494f1cc8 100644 > --- a/include/drm/drm_dsc.h > +++ b/include/drm/drm_dsc.h > @@ -481,5 +481,6 @@ struct drm_dsc_pps_infoframe { > void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp); > void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, > const struct drm_dsc_config *dsc_cfg); > +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); > > #endif /* _DRM_DSC_H_ */ > -- > 2.17.1 >
Hi David, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on linus/master] [also build test WARNING on v5.0-rc4 next-20190213] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/David-Francis/Make-DRM-DSC-helpers-more-generally-usable/20190214-052541 reproduce: make htmldocs All warnings (new ones prefixed by >>): net/mac80211/sta_info.h:590: warning: Function parameter or member 'tx_stats.last_rate' not described in 'sta_info' net/mac80211/sta_info.h:590: warning: Function parameter or member 'tx_stats.msdu' not described in 'sta_info' kernel/rcu/tree.c:711: warning: Excess function parameter 'irq' description in 'rcu_nmi_exit' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.cb' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.poll' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.active' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.cb' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.poll' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.active' not described in 'dma_buf' include/linux/dma-fence-array.h:54: warning: Function parameter or member 'work' not described in 'dma_fence_array' include/linux/firmware/intel/stratix10-svc-client.h:1: warning: no structured comments found include/linux/gpio/driver.h:371: warning: Function parameter or member 'init_valid_mask' not described in 'gpio_chip' include/linux/iio/hw-consumer.h:1: warning: no structured comments found include/linux/input/sparse-keymap.h:46: warning: Function parameter or member 'sw' not described in 'key_entry' drivers/mtd/nand/raw/nand_base.c:420: warning: Function parameter or member 'chip' not described in 'nand_fill_oob' drivers/mtd/nand/raw/nand_bbt.c:173: warning: Function parameter or member 'this' not described in 'read_bbt' drivers/mtd/nand/raw/nand_bbt.c:173: warning: Excess function parameter 'chip' description in 'read_bbt' include/linux/regulator/machine.h:199: warning: Function parameter or member 'max_uV_step' not described in 'regulation_constraints' include/linux/regulator/driver.h:228: warning: Function parameter or member 'resume' not described in 'regulator_ops' arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw0' not described in 'irb' arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw1' not described in 'irb' arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw2' not described in 'irb' arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw3' not described in 'irb' arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.eadm' not described in 'irb' drivers/slimbus/stream.c:1: warning: no structured comments found include/linux/spi/spi.h:180: warning: Function parameter or member 'driver_override' not described in 'spi_device' drivers/target/target_core_device.c:1: warning: no structured comments found drivers/usb/typec/bus.c:1: warning: no structured comments found drivers/usb/typec/class.c:1: warning: no structured comments found include/linux/w1.h:281: warning: Function parameter or member 'of_match_table' not described in 'w1_family' fs/direct-io.c:257: warning: Excess function parameter 'offset' description in 'dio_complete' fs/file_table.c:1: warning: no structured comments found fs/libfs.c:477: warning: Excess function parameter 'available' description in 'simple_write_end' fs/posix_acl.c:646: warning: Function parameter or member 'inode' not described in 'posix_acl_update_mode' fs/posix_acl.c:646: warning: Function parameter or member 'mode_p' not described in 'posix_acl_update_mode' fs/posix_acl.c:646: warning: Function parameter or member 'acl' not described in 'posix_acl_update_mode' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_end' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_end' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_end' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:183: warning: Function parameter or member 'blockable' not described in 'amdgpu_mn_read_lock' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Function parameter or member 'range' not described in 'amdgpu_mn_invalidate_range_start_hsa' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Function parameter or member 'range' not described in 'amdgpu_mn_invalidate_range_end' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_end' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_end' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_end' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:382: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor ' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:383: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor ' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:555: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_leaf' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:555: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_leaf' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:555: warning: Function parameter or member 'start' not described in 'for_each_amdgpu_vm_pt_leaf' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:555: warning: Function parameter or member 'end' not described in 'for_each_amdgpu_vm_pt_leaf' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:555: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_leaf' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:603: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_dfs_safe' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:603: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_dfs_safe' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:603: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_dfs_safe' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:603: warning: Function parameter or member 'entry' not described in 'for_each_amdgpu_vm_pt_dfs_safe' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:845: warning: Function parameter or member 'level' not described in 'amdgpu_vm_bo_param' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_func' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_func' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_func' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_func' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_func' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_func' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_func' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_huge' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_huge' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'level' not described in 'amdgpu_vm_update_huge' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_huge' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_huge' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_huge' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_huge' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_huge' drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:3093: warning: Function parameter or member 'pasid' not described in 'amdgpu_vm_make_compute' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:128: warning: Incorrect use of kernel-doc format: Documentation Makefile include scripts source @atomic_obj drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'atomic_obj' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'atomic_obj_lock' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'backlight_link' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'backlight_caps' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'freesync_module' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'fw_dmcu' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'dmcu_fw_version' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:1: warning: no structured comments found include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_pin' not described in 'drm_driver' include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_unpin' not described in 'drm_driver' include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_res_obj' not described in 'drm_driver' include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_get_sg_table' not described in 'drm_driver' include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_import_sg_table' not described in 'drm_driver' include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_vmap' not described in 'drm_driver' include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_vunmap' not described in 'drm_driver' include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_mmap' not described in 'drm_driver' include/drm/drm_atomic_state_helper.h:1: warning: no structured comments found drivers/gpu/drm/drm_dp_helper.c:1364: warning: Function parameter or member 'dsc_dpcd' not described in 'drm_dp_dsc_sink_max_slice_count' drivers/gpu/drm/drm_dp_helper.c:1364: warning: Function parameter or member 'is_edp' not described in 'drm_dp_dsc_sink_max_slice_count' drivers/gpu/drm/drm_dsc.c:240: warning: Excess function parameter 'dsc_cfg' description in 'drm_dsc_compute_rc_parameters' >> drivers/gpu/drm/drm_dsc.c:241: warning: Function parameter or member 'vdsc_cfg' not described in 'drm_dsc_compute_rc_parameters' drivers/gpu/drm/drm_dsc.c:241: warning: Excess function parameter 'dsc_cfg' description in 'drm_dsc_compute_rc_parameters' drivers/gpu/drm/i915/i915_vma.h:49: warning: cannot understand function prototype: 'struct i915_vma ' drivers/gpu/drm/i915/i915_vma.h:1: warning: no structured comments found drivers/gpu/drm/i915/intel_guc_fwif.h:536: warning: cannot understand function prototype: 'struct guc_log_buffer_state ' drivers/gpu/drm/i915/i915_trace.h:1: warning: no structured comments found include/linux/skbuff.h:876: warning: Function parameter or member 'dev_scratch' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'list' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'ip_defrag_offset' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'skb_mstamp_ns' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member '__cloned_offset' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'head_frag' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member '__pkt_type_offset' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'encapsulation' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'encap_hdr_csum' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'csum_valid' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member '__pkt_vlan_present_offset' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'vlan_present' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'csum_complete_sw' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'csum_level' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'inner_protocol_type' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'remcsum_offload' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'sender_cpu' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'reserved_tailroom' not described in 'sk_buff' include/linux/skbuff.h:876: warning: Function parameter or member 'inner_ipproto' not described in 'sk_buff' include/net/sock.h:238: warning: Function parameter or member 'skc_addrpair' not described in 'sock_common' include/net/sock.h:238: warning: Function parameter or member 'skc_portpair' not described in 'sock_common' include/net/sock.h:238: warning: Function parameter or member 'skc_ipv6only' not described in 'sock_common' include/net/sock.h:238: warning: Function parameter or member 'skc_net_refcnt' not described in 'sock_common' include/net/sock.h:238: warning: Function parameter or member 'skc_v6_daddr' not described in 'sock_common' include/net/sock.h:238: warning: Function parameter or member 'skc_v6_rcv_saddr' not described in 'sock_common' include/net/sock.h:238: warning: Function parameter or member 'skc_cookie' not described in 'sock_common' include/net/sock.h:238: warning: Function parameter or member 'skc_listener' not described in 'sock_common' include/net/sock.h:238: warning: Function parameter or member 'skc_tw_dr' not described in 'sock_common' include/net/sock.h:238: warning: Function parameter or member 'skc_rcv_wnd' not described in 'sock_common' include/net/sock.h:238: warning: Function parameter or member 'skc_tw_rcv_nxt' not described in 'sock_common' include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.rmem_alloc' not described in 'sock' include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.len' not described in 'sock' include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.head' not described in 'sock' include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.tail' not described in 'sock' include/net/sock.h:513: warning: Function parameter or member 'sk_wq_raw' not described in 'sock' include/net/sock.h:513: warning: Function parameter or member 'tcp_rtx_queue' not described in 'sock' include/net/sock.h:513: warning: Function parameter or member 'sk_route_forced_caps' not described in 'sock' include/net/sock.h:513: warning: Function parameter or member 'sk_txtime_report_errors' not described in 'sock' include/net/sock.h:513: warning: Function parameter or member 'sk_validate_xmit_skb' not described in 'sock' include/linux/netdevice.h:2048: warning: Function parameter or member 'adj_list.upper' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'adj_list.lower' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'gso_partial_features' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'switchdev_ops' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'l3mdev_ops' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'xfrmdev_ops' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'tlsdev_ops' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'name_assign_type' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'ieee802154_ptr' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'mpls_ptr' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'xdp_prog' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'gro_flush_timeout' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'nf_hooks_ingress' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member '____cacheline_aligned_in_smp' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'qdisc_hash' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'xps_cpus_map' not described in 'net_device' include/linux/netdevice.h:2048: warning: Function parameter or member 'xps_rxqs_map' not described in 'net_device' include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising' not described in 'phylink_link_state' include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising' not described in 'phylink_link_state' Documentation/admin-guide/cgroup-v2.rst:1509: WARNING: Block quote ends without a blank line; unexpected unindent. Documentation/admin-guide/cgroup-v2.rst:1511: WARNING: Block quote ends without a blank line; unexpected unindent. Documentation/admin-guide/cgroup-v2.rst:1512: WARNING: Block quote ends without a blank line; unexpected unindent. include/linux/interrupt.h:252: WARNING: Inline emphasis start-string without end-string. include/net/mac80211.h:1214: ERROR: Unexpected indentation. include/net/mac80211.h:1221: WARNING: Block quote ends without a blank line; unexpected unindent. include/linux/wait.h:110: WARNING: Block quote ends without a blank line; unexpected unindent. include/linux/wait.h:113: ERROR: Unexpected indentation. include/linux/wait.h:115: WARNING: Block quote ends without a blank line; unexpected unindent. kernel/time/hrtimer.c:1120: WARNING: Block quote ends without a blank line; unexpected unindent. kernel/signal.c:344: WARNING: Inline literal start-string without end-string. include/linux/kernel.h:137: WARNING: Inline interpreted text or phrase reference start-string without end-string. Documentation/driver-api/dmaengine/dmatest.rst:63: ERROR: Unexpected indentation. include/uapi/linux/firewire-cdev.h:312: WARNING: Inline literal start-string without end-string. Documentation/driver-api/gpio/board.rst:209: ERROR: Unexpected indentation. drivers/ata/libata-core.c:5959: ERROR: Unknown target name: "hw". drivers/message/fusion/mptbase.c:5057: WARNING: Definition list ends without a blank line; unexpected unindent. drivers/tty/serial/serial_core.c:1952: WARNING: Definition list ends without a blank line; unexpected unindent. include/linux/mtd/rawnand.h:1192: WARNING: Inline strong start-string without end-string. include/linux/mtd/rawnand.h:1194: WARNING: Inline strong start-string without end-string. include/linux/regulator/driver.h:287: ERROR: Unknown target name: "regulator_regmap_x_voltage". Documentation/driver-api/soundwire/locking.rst:50: ERROR: Inconsistent literal block quoting. Documentation/driver-api/soundwire/locking.rst:51: WARNING: Line block ends without a blank line. Documentation/driver-api/soundwire/locking.rst:55: WARNING: Inline substitution_reference start-string without end-string. Documentation/driver-api/soundwire/locking.rst:56: WARNING: Line block ends without a blank line. include/linux/spi/spi.h:368: ERROR: Unexpected indentation. fs/posix_acl.c:635: WARNING: Inline emphasis start-string without end-string. Documentation/filesystems/path-lookup.rst:347: WARNING: Title underline too short. vim +241 drivers/gpu/drm/drm_dsc.c 230 231 /** 232 * drm_dsc_compute_rc_parameters() - Write rate control 233 * parameters to the dsc configuration. Some configuration 234 * fields must be present beforehand. 235 * 236 * @dsc_cfg: 237 * DSC Configuration data partially filled by driver 238 */ 239 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) > 240 { > 241 unsigned long groups_per_line = 0; --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
Hi David,
url: https://github.com/0day-ci/linux/commits/David-Francis/Make-DRM-DSC-helpers-more-generally-usable/20190214-052541
smatch warnings:
drivers/gpu/drm/drm_dsc.c:306 drm_dsc_compute_rc_parameters() warn: impossible condition '(vdsc_cfg->nfl_bpg_offset > 65535) => (0-u16max > u16max)'
drivers/gpu/drm/drm_dsc.c:340 drm_dsc_compute_rc_parameters() warn: impossible condition '(vdsc_cfg->scale_increment_interval > 65535) => (0-u16max > u16max)'
# https://github.com/0day-ci/linux/commit/932e204c9cbe2995451a800351bcd781fa7cb1c5
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout 932e204c9cbe2995451a800351bcd781fa7cb1c5
vim +306 drivers/gpu/drm/drm_dsc.c
932e204c David Francis 2019-02-13 230
932e204c David Francis 2019-02-13 231 /**
932e204c David Francis 2019-02-13 232 * drm_dsc_compute_rc_parameters() - Write rate control
932e204c David Francis 2019-02-13 233 * parameters to the dsc configuration. Some configuration
932e204c David Francis 2019-02-13 234 * fields must be present beforehand.
932e204c David Francis 2019-02-13 235 *
932e204c David Francis 2019-02-13 236 * @dsc_cfg:
932e204c David Francis 2019-02-13 237 * DSC Configuration data partially filled by driver
932e204c David Francis 2019-02-13 238 */
932e204c David Francis 2019-02-13 239 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
932e204c David Francis 2019-02-13 240 {
932e204c David Francis 2019-02-13 241 unsigned long groups_per_line = 0;
932e204c David Francis 2019-02-13 242 unsigned long groups_total = 0;
932e204c David Francis 2019-02-13 243 unsigned long num_extra_mux_bits = 0;
932e204c David Francis 2019-02-13 244 unsigned long slice_bits = 0;
932e204c David Francis 2019-02-13 245 unsigned long hrd_delay = 0;
932e204c David Francis 2019-02-13 246 unsigned long final_scale = 0;
932e204c David Francis 2019-02-13 247 unsigned long rbs_min = 0;
932e204c David Francis 2019-02-13 248
932e204c David Francis 2019-02-13 249 /* Number of groups used to code each line of a slice */
932e204c David Francis 2019-02-13 250 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
932e204c David Francis 2019-02-13 251 DSC_RC_PIXELS_PER_GROUP);
932e204c David Francis 2019-02-13 252
932e204c David Francis 2019-02-13 253 /* chunksize in Bytes */
932e204c David Francis 2019-02-13 254 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
932e204c David Francis 2019-02-13 255 vdsc_cfg->bits_per_pixel,
932e204c David Francis 2019-02-13 256 (8 * 16));
932e204c David Francis 2019-02-13 257
932e204c David Francis 2019-02-13 258 if (vdsc_cfg->convert_rgb)
932e204c David Francis 2019-02-13 259 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
932e204c David Francis 2019-02-13 260 (4 * vdsc_cfg->bits_per_component + 4)
932e204c David Francis 2019-02-13 261 - 2);
932e204c David Francis 2019-02-13 262 else
932e204c David Francis 2019-02-13 263 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
932e204c David Francis 2019-02-13 264 (4 * vdsc_cfg->bits_per_component + 4) +
932e204c David Francis 2019-02-13 265 2 * (4 * vdsc_cfg->bits_per_component) - 2;
932e204c David Francis 2019-02-13 266 /* Number of bits in one Slice */
932e204c David Francis 2019-02-13 267 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
932e204c David Francis 2019-02-13 268
932e204c David Francis 2019-02-13 269 while ((num_extra_mux_bits > 0) &&
932e204c David Francis 2019-02-13 270 ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
932e204c David Francis 2019-02-13 271 num_extra_mux_bits--;
932e204c David Francis 2019-02-13 272
932e204c David Francis 2019-02-13 273 if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
932e204c David Francis 2019-02-13 274 vdsc_cfg->initial_scale_value = groups_per_line + 8;
932e204c David Francis 2019-02-13 275
932e204c David Francis 2019-02-13 276 /* scale_decrement_interval calculation according to DSC spec 1.11 */
932e204c David Francis 2019-02-13 277 if (vdsc_cfg->initial_scale_value > 8)
932e204c David Francis 2019-02-13 278 vdsc_cfg->scale_decrement_interval = groups_per_line /
932e204c David Francis 2019-02-13 279 (vdsc_cfg->initial_scale_value - 8);
932e204c David Francis 2019-02-13 280 else
932e204c David Francis 2019-02-13 281 vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
932e204c David Francis 2019-02-13 282
932e204c David Francis 2019-02-13 283 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
932e204c David Francis 2019-02-13 284 (vdsc_cfg->initial_xmit_delay *
932e204c David Francis 2019-02-13 285 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
932e204c David Francis 2019-02-13 286
932e204c David Francis 2019-02-13 287 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
932e204c David Francis 2019-02-13 288 DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
932e204c David Francis 2019-02-13 289 return -ERANGE;
932e204c David Francis 2019-02-13 290 }
932e204c David Francis 2019-02-13 291
932e204c David Francis 2019-02-13 292 final_scale = (vdsc_cfg->rc_model_size * 8) /
932e204c David Francis 2019-02-13 293 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
932e204c David Francis 2019-02-13 294 if (vdsc_cfg->slice_height > 1)
932e204c David Francis 2019-02-13 295 /*
932e204c David Francis 2019-02-13 296 * NflBpgOffset is 16 bit value with 11 fractional bits
932e204c David Francis 2019-02-13 297 * hence we multiply by 2^11 for preserving the
932e204c David Francis 2019-02-13 298 * fractional part
932e204c David Francis 2019-02-13 299 */
932e204c David Francis 2019-02-13 300 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
932e204c David Francis 2019-02-13 301 (vdsc_cfg->slice_height - 1));
932e204c David Francis 2019-02-13 302 else
932e204c David Francis 2019-02-13 303 vdsc_cfg->nfl_bpg_offset = 0;
932e204c David Francis 2019-02-13 304
932e204c David Francis 2019-02-13 305 /* 2^16 - 1 */
932e204c David Francis 2019-02-13 @306 if (vdsc_cfg->nfl_bpg_offset > 65535) {
932e204c David Francis 2019-02-13 307 DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
932e204c David Francis 2019-02-13 308 return -ERANGE;
932e204c David Francis 2019-02-13 309 }
932e204c David Francis 2019-02-13 310
932e204c David Francis 2019-02-13 311 /* Number of groups used to code the entire slice */
932e204c David Francis 2019-02-13 312 groups_total = groups_per_line * vdsc_cfg->slice_height;
932e204c David Francis 2019-02-13 313
932e204c David Francis 2019-02-13 314 /* slice_bpg_offset is 16 bit value with 11 fractional bits */
932e204c David Francis 2019-02-13 315 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
932e204c David Francis 2019-02-13 316 vdsc_cfg->initial_offset +
932e204c David Francis 2019-02-13 317 num_extra_mux_bits) << 11),
932e204c David Francis 2019-02-13 318 groups_total);
932e204c David Francis 2019-02-13 319
932e204c David Francis 2019-02-13 320 if (final_scale > 9) {
932e204c David Francis 2019-02-13 321 /*
932e204c David Francis 2019-02-13 322 * ScaleIncrementInterval =
932e204c David Francis 2019-02-13 323 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
932e204c David Francis 2019-02-13 324 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
932e204c David Francis 2019-02-13 325 * we need divide by 2^11 from pstDscCfg values
932e204c David Francis 2019-02-13 326 */
932e204c David Francis 2019-02-13 327 vdsc_cfg->scale_increment_interval =
932e204c David Francis 2019-02-13 328 (vdsc_cfg->final_offset * (1 << 11)) /
932e204c David Francis 2019-02-13 329 ((vdsc_cfg->nfl_bpg_offset +
932e204c David Francis 2019-02-13 330 vdsc_cfg->slice_bpg_offset) *
932e204c David Francis 2019-02-13 331 (final_scale - 9));
932e204c David Francis 2019-02-13 332 } else {
932e204c David Francis 2019-02-13 333 /*
932e204c David Francis 2019-02-13 334 * If finalScaleValue is less than or equal to 9, a value of 0 should
932e204c David Francis 2019-02-13 335 * be used to disable the scale increment at the end of the slice
932e204c David Francis 2019-02-13 336 */
932e204c David Francis 2019-02-13 337 vdsc_cfg->scale_increment_interval = 0;
932e204c David Francis 2019-02-13 338 }
932e204c David Francis 2019-02-13 339
932e204c David Francis 2019-02-13 @340 if (vdsc_cfg->scale_increment_interval > 65535) {
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c index bc2b23adb072..4b0e3c9c3ff8 100644 --- a/drivers/gpu/drm/drm_dsc.c +++ b/drivers/gpu/drm/drm_dsc.c @@ -11,6 +11,7 @@ #include <linux/init.h> #include <linux/errno.h> #include <linux/byteorder/generic.h> +#include <drm/drm_print.h> #include <drm/drm_dp_helper.h> #include <drm/drm_dsc.h> @@ -226,3 +227,135 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, /* PPS 94 - 127 are O */ } EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack); + +/** + * drm_dsc_compute_rc_parameters() - Write rate control + * parameters to the dsc configuration. Some configuration + * fields must be present beforehand. + * + * @dsc_cfg: + * DSC Configuration data partially filled by driver + */ +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) +{ + unsigned long groups_per_line = 0; + unsigned long groups_total = 0; + unsigned long num_extra_mux_bits = 0; + unsigned long slice_bits = 0; + unsigned long hrd_delay = 0; + unsigned long final_scale = 0; + unsigned long rbs_min = 0; + + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + + if (vdsc_cfg->convert_rgb) + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + - 2); + else + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 2 * (4 * vdsc_cfg->bits_per_component) - 2; + /* Number of bits in one Slice */ + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; + + while ((num_extra_mux_bits > 0) && + ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) + num_extra_mux_bits--; + + if (groups_per_line < vdsc_cfg->initial_scale_value - 8) + vdsc_cfg->initial_scale_value = groups_per_line + 8; + + /* scale_decrement_interval calculation according to DSC spec 1.11 */ + if (vdsc_cfg->initial_scale_value > 8) + vdsc_cfg->scale_decrement_interval = groups_per_line / + (vdsc_cfg->initial_scale_value - 8); + else + vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; + + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - + (vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; + + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { + DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); + return -ERANGE; + } + + final_scale = (vdsc_cfg->rc_model_size * 8) / + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); + if (vdsc_cfg->slice_height > 1) + /* + * NflBpgOffset is 16 bit value with 11 fractional bits + * hence we multiply by 2^11 for preserving the + * fractional part + */ + vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), + (vdsc_cfg->slice_height - 1)); + else + vdsc_cfg->nfl_bpg_offset = 0; + + /* 2^16 - 1 */ + if (vdsc_cfg->nfl_bpg_offset > 65535) { + DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n"); + return -ERANGE; + } + + /* Number of groups used to code the entire slice */ + groups_total = groups_per_line * vdsc_cfg->slice_height; + + /* slice_bpg_offset is 16 bit value with 11 fractional bits */ + vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - + vdsc_cfg->initial_offset + + num_extra_mux_bits) << 11), + groups_total); + + if (final_scale > 9) { + /* + * ScaleIncrementInterval = + * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) + * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, + * we need divide by 2^11 from pstDscCfg values + */ + vdsc_cfg->scale_increment_interval = + (vdsc_cfg->final_offset * (1 << 11)) / + ((vdsc_cfg->nfl_bpg_offset + + vdsc_cfg->slice_bpg_offset) * + (final_scale - 9)); + } else { + /* + * If finalScaleValue is less than or equal to 9, a value of 0 should + * be used to disable the scale increment at the end of the slice + */ + vdsc_cfg->scale_increment_interval = 0; + } + + if (vdsc_cfg->scale_increment_interval > 65535) { + DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n"); + return -ERANGE; + } + + /* + * DSC spec mentions that bits_per_pixel specifies the target + * bits/pixel (bpp) rate that is used by the encoder, + * in steps of 1/16 of a bit per pixel + */ + rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + + DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel, 16) + + groups_per_line * vdsc_cfg->first_line_bpg_offset; + + hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); + vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; + vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; + + return 0; +} +EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index c56ba0e04044..c76cec8bfb74 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -318,129 +318,6 @@ static int get_column_index_for_rc_params(u8 bits_per_component) } } -static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) -{ - unsigned long groups_per_line = 0; - unsigned long groups_total = 0; - unsigned long num_extra_mux_bits = 0; - unsigned long slice_bits = 0; - unsigned long hrd_delay = 0; - unsigned long final_scale = 0; - unsigned long rbs_min = 0; - - /* Number of groups used to code each line of a slice */ - groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, - DSC_RC_PIXELS_PER_GROUP); - - /* chunksize in Bytes */ - vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * - vdsc_cfg->bits_per_pixel, - (8 * 16)); - - if (vdsc_cfg->convert_rgb) - num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + - (4 * vdsc_cfg->bits_per_component + 4) - - 2); - else - num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + - (4 * vdsc_cfg->bits_per_component + 4) + - 2 * (4 * vdsc_cfg->bits_per_component) - 2; - /* Number of bits in one Slice */ - slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; - - while ((num_extra_mux_bits > 0) && - ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) - num_extra_mux_bits--; - - if (groups_per_line < vdsc_cfg->initial_scale_value - 8) - vdsc_cfg->initial_scale_value = groups_per_line + 8; - - /* scale_decrement_interval calculation according to DSC spec 1.11 */ - if (vdsc_cfg->initial_scale_value > 8) - vdsc_cfg->scale_decrement_interval = groups_per_line / - (vdsc_cfg->initial_scale_value - 8); - else - vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; - - vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - - (vdsc_cfg->initial_xmit_delay * - vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; - - if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { - DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); - return -ERANGE; - } - - final_scale = (vdsc_cfg->rc_model_size * 8) / - (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); - if (vdsc_cfg->slice_height > 1) - /* - * NflBpgOffset is 16 bit value with 11 fractional bits - * hence we multiply by 2^11 for preserving the - * fractional part - */ - vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), - (vdsc_cfg->slice_height - 1)); - else - vdsc_cfg->nfl_bpg_offset = 0; - - /* 2^16 - 1 */ - if (vdsc_cfg->nfl_bpg_offset > 65535) { - DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n"); - return -ERANGE; - } - - /* Number of groups used to code the entire slice */ - groups_total = groups_per_line * vdsc_cfg->slice_height; - - /* slice_bpg_offset is 16 bit value with 11 fractional bits */ - vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - - vdsc_cfg->initial_offset + - num_extra_mux_bits) << 11), - groups_total); - - if (final_scale > 9) { - /* - * ScaleIncrementInterval = - * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) - * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, - * we need divide by 2^11 from pstDscCfg values - */ - vdsc_cfg->scale_increment_interval = - (vdsc_cfg->final_offset * (1 << 11)) / - ((vdsc_cfg->nfl_bpg_offset + - vdsc_cfg->slice_bpg_offset) * - (final_scale - 9)); - } else { - /* - * If finalScaleValue is less than or equal to 9, a value of 0 should - * be used to disable the scale increment at the end of the slice - */ - vdsc_cfg->scale_increment_interval = 0; - } - - if (vdsc_cfg->scale_increment_interval > 65535) { - DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n"); - return -ERANGE; - } - - /* - * DSC spec mentions that bits_per_pixel specifies the target - * bits/pixel (bpp) rate that is used by the encoder, - * in steps of 1/16 of a bit per pixel - */ - rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + - DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * - vdsc_cfg->bits_per_pixel, 16) + - groups_per_line * vdsc_cfg->first_line_bpg_offset; - - hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); - vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; - vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; - - return 0; -} - int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config) { @@ -575,7 +452,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); - return intel_compute_rc_parameters(vdsc_cfg); + return drm_dsc_compute_rc_parameters(vdsc_cfg); } enum intel_display_power_domain diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index d03f1b83421a..ad43494f1cc8 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -481,5 +481,6 @@ struct drm_dsc_pps_infoframe { void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp); void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp, const struct drm_dsc_config *dsc_cfg); +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); #endif /* _DRM_DSC_H_ */
The function intel_compute_rc_parameters is part of the dsc spec and is not driver-specific. Other drm drivers might like to use it. The function is not changed; just moved and renamed. Signed-off-by: David Francis <David.Francis@amd.com> --- drivers/gpu/drm/drm_dsc.c | 133 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_vdsc.c | 125 +--------------------------- include/drm/drm_dsc.h | 1 + 3 files changed, 135 insertions(+), 124 deletions(-)