| Message ID | 20190403233539.31828-1-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment | expand |
On Wed, Apr 03, 2019 at 04:35:33PM -0700, José Roberto de Souza wrote: > Turn out it is not a DMC bug it is actually a HW one, so this > workaround will be needed for current gens, lets update the comment > and remove the FIXME. Do we have a Wa #number for this? p[art of workaround page or just part of programming sequence? > > BSpec: 7723 > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index ec874d802d48..c80bb3003a7d 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -531,10 +531,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > val |= EDP_PSR2_TP2_TIME_2500us; > > /* > - * FIXME: There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin > - * and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after > - * exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now > - * lets workaround the issue by cleaning PSR_CTL before enable PSR2. > + * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > + * recommending keep this bit unset while PSR2 is enabled. > */ > I915_WRITE(EDP_PSR_CTL, 0); > > -- > 2.21.0 >
I update the Bspec as general programming. SRD_CTL TP2 TP3 Select - "This bit impacts PSR2. Clear it before enabling PSR2 and do not set it while PSR2 is enabled." I haven't seen the hardware bug report come through yet to establish the wa number. > -----Original Message----- > From: Vivi, Rodrigo > Sent: Wednesday, 3 April, 2019 5:22 PM > To: Souza, Jose <jose.souza@intel.com>; Runyan, Arthur J > <arthur.j.runyan@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > <dhinakaran.pandiyan@intel.com> > Subject: Re: [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround > comment > > On Wed, Apr 03, 2019 at 04:35:33PM -0700, José Roberto de Souza wrote: > > Turn out it is not a DMC bug it is actually a HW one, so this > > workaround will be needed for current gens, lets update the comment > > and remove the FIXME. > > Do we have a Wa #number for this? p[art of workaround page > or just part of programming sequence? > > > > > BSpec: 7723 > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/intel_psr.c | 6 ++---- > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > > index ec874d802d48..c80bb3003a7d 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -531,10 +531,8 @@ static void hsw_activate_psr2(struct intel_dp > *intel_dp) > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > /* > > - * FIXME: There is probably a issue in DMC > firmwares(icl_dmc_ver1_07.bin > > - * and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after > > - * exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now > > - * lets workaround the issue by cleaning PSR_CTL before enable PSR2. > > + * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > > + * recommending keep this bit unset while PSR2 is enabled. > > */ > > I915_WRITE(EDP_PSR_CTL, 0); > > > > -- > > 2.21.0 > >
On Wed, Apr 03, 2019 at 05:39:40PM -0700, Runyan, Arthur J wrote: > I update the Bspec as general programming. SRD_CTL TP2 TP3 Select - "This bit impacts PSR2. Clear it before enabling PSR2 and do not set it while PSR2 is enabled." > I haven't seen the hardware bug report come through yet to establish the wa number. Thanks Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > -----Original Message----- > > From: Vivi, Rodrigo > > Sent: Wednesday, 3 April, 2019 5:22 PM > > To: Souza, Jose <jose.souza@intel.com>; Runyan, Arthur J > > <arthur.j.runyan@intel.com> > > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > > <dhinakaran.pandiyan@intel.com> > > Subject: Re: [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround > > comment > > > > On Wed, Apr 03, 2019 at 04:35:33PM -0700, José Roberto de Souza wrote: > > > Turn out it is not a DMC bug it is actually a HW one, so this > > > workaround will be needed for current gens, lets update the comment > > > and remove the FIXME. > > > > Do we have a Wa #number for this? p[art of workaround page > > or just part of programming sequence? > > > > > > > > BSpec: 7723 > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > --- > > > drivers/gpu/drm/i915/intel_psr.c | 6 ++---- > > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > > index ec874d802d48..c80bb3003a7d 100644 > > > --- a/drivers/gpu/drm/i915/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > > @@ -531,10 +531,8 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > > > /* > > > - * FIXME: There is probably a issue in DMC > > firmwares(icl_dmc_ver1_07.bin > > > - * and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after > > > - * exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now > > > - * lets workaround the issue by cleaning PSR_CTL before enable PSR2. > > > + * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > > > + * recommending keep this bit unset while PSR2 is enabled. > > > */ > > > I915_WRITE(EDP_PSR_CTL, 0); > > > > > > -- > > > 2.21.0 > > >
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index ec874d802d48..c80bb3003a7d 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -531,10 +531,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_TP2_TIME_2500us; /* - * FIXME: There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin - * and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after - * exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now - * lets workaround the issue by cleaning PSR_CTL before enable PSR2. + * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is + * recommending keep this bit unset while PSR2 is enabled. */ I915_WRITE(EDP_PSR_CTL, 0);
Turn out it is not a DMC bug it is actually a HW one, so this workaround will be needed for current gens, lets update the comment and remove the FIXME. BSpec: 7723 Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)