diff mbox series

[09/28] drm/i915/tgl: Check if pipe D is fused

Message ID 20190625175437.14840-10-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Initial support for Tiger Lake | expand

Commit Message

Lucas De Marchi June 25, 2019, 5:54 p.m. UTC 
From: José Roberto de Souza <jose.souza@intel.com>

On Tiger Lake there is one more pipe - check if it's fused.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_device_info.c | 3 +++
 2 files changed, 4 insertions(+)

Comments

Srivatsa, Anusha June 26, 2019, 9:24 p.m. UTC | #1 
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Lucas De Marchi
>Sent: Tuesday, June 25, 2019 10:54 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
>Subject: [Intel-gfx] [PATCH 09/28] drm/i915/tgl: Check if pipe D is fused
>
>From: José Roberto de Souza <jose.souza@intel.com>
>
>On Tiger Lake there is one more pipe - check if it's fused.
>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

>---
> drivers/gpu/drm/i915/i915_reg.h          | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 3 +++
> 2 files changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index a63a337eec2c..95fdc8dbca31 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7618,6 +7618,7 @@ enum {
> #define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
>+#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
>
> #define SKL_DSSM				_MMIO(0x51004)
> #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c
>b/drivers/gpu/drm/i915/intel_device_info.c
>index e0d9a7a37994..f99c9fd497b2 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -938,6 +938,9 @@ void intel_device_info_runtime_init(struct
>drm_i915_private *dev_priv)
> 			enabled_mask &= ~BIT(PIPE_B);
> 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> 			enabled_mask &= ~BIT(PIPE_C);
>+		if (INTEL_GEN(dev_priv) >= 12 &&
>+		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
>+			enabled_mask &= ~BIT(PIPE_D);
>
> 		/*
> 		 * At least one pipe should be enabled and if there are
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a63a337eec2c..95fdc8dbca31 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7618,6 +7618,7 @@  enum {
 #define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
 #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
+#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
 
 #define SKL_DSSM				_MMIO(0x51004)
 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e0d9a7a37994..f99c9fd497b2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -938,6 +938,9 @@  void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 			enabled_mask &= ~BIT(PIPE_B);
 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
 			enabled_mask &= ~BIT(PIPE_C);
+		if (INTEL_GEN(dev_priv) >= 12 &&
+		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
+			enabled_mask &= ~BIT(PIPE_D);
 
 		/*
 		 * At least one pipe should be enabled and if there are