diff mbox series

[3/3] drm/i915/tgl: Implement Wa_1406941453

Message ID 20190726000226.26914-4-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Tiger Lake: add workarounds | expand

Commit Message

Lucas De Marchi July 26, 2019, 12:02 a.m. UTC 
From: Michel Thierry <michel.thierry@intel.com>

Enable Small PL for power benefit.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-18-lucas.demarchi@intel.com
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
 drivers/gpu/drm/i915/i915_reg.h             | 3 +++
 2 files changed, 8 insertions(+)

Comments

Sripada, Radhakrishna Aug. 12, 2019, 10:10 p.m. UTC | #1 
On Thu, Jul 25, 2019 at 05:02:26PM -0700, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Enable Small PL for power benefit.
> 
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-18-lucas.demarchi@intel.com
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
>  drivers/gpu/drm/i915/i915_reg.h             | 3 +++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3235ef355dfd..830ccd416a29 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1279,6 +1279,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  		wa_write_or(wal,
>  			    GEN12_L3SQCREG2,
>  			    GEN12_LQSC_FLUSH_COHERENT_LINES);
> +
> +		/* Wa_1406941453:tgl */
> +		wa_masked_en(wal,
> +			     SAMPLER_MODE,
> +			     SAMPLER_ENABLE_SMALL_PL);
>  	}
>  
>  	if (IS_GEN(i915, 11)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fbbb89f6ca2f..71efb37f54a3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8965,6 +8965,9 @@ enum {
>  #define   GEN9_DG_MIRROR_FIX_ENABLE	(1 << 5)
>  #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1 << 3)
>  
> +#define SAMPLER_MODE			_MMIO(0xe18c)
> +#define   SAMPLER_ENABLE_SMALL_PL	(1 << 15)
> +
>  #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
>  #define   FLOW_CONTROL_ENABLE		(1 << 15)
>  #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1 << 8)
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3235ef355dfd..830ccd416a29 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1279,6 +1279,11 @@  rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		wa_write_or(wal,
 			    GEN12_L3SQCREG2,
 			    GEN12_LQSC_FLUSH_COHERENT_LINES);
+
+		/* Wa_1406941453:tgl */
+		wa_masked_en(wal,
+			     SAMPLER_MODE,
+			     SAMPLER_ENABLE_SMALL_PL);
 	}
 
 	if (IS_GEN(i915, 11)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbbb89f6ca2f..71efb37f54a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8965,6 +8965,9 @@  enum {
 #define   GEN9_DG_MIRROR_FIX_ENABLE	(1 << 5)
 #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1 << 3)
 
+#define SAMPLER_MODE			_MMIO(0xe18c)
+#define   SAMPLER_ENABLE_SMALL_PL	(1 << 15)
+
 #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
 #define   FLOW_CONTROL_ENABLE		(1 << 15)
 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1 << 8)