diff mbox series

[3/4] drm/i915/tgl: Tigerlake only has global MOCS registers

Message ID 20190726001208.6971-4-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Tiger Lake: MOCS table handling | expand

Commit Message

Lucas De Marchi July 26, 2019, 12:12 a.m. UTC 
From: Michel Thierry <michel.thierry@intel.com>

Until Icelake, each engine had its own set of 64 MOCS registers. In
order to simplify, Tigerlake moves to only 64 Global MOCS registers,
which are no longer part of the engine context. Since these registers
are now global, they also only need to be initialized once.

From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU
management (5:4) fields and cannot be programmed to 'use the value from
Private PAT', because these fields are no longer part of the PPAT. Also
cacheability control (1:0) field has changed, 00 no longer means 'use
controls from page table', but uncacheable (UC).

v2: Move the changes to the fault registers to a separate commit - the old ones
    overlap with the range used by the new global MOCS (requested by
    Daniele)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c     | 47 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_mocs.h     |  1 +
 drivers/gpu/drm/i915/i915_drv.h          |  2 +
 drivers/gpu/drm/i915/i915_gem.c          |  1 +
 drivers/gpu/drm/i915/i915_gpu_error.c    |  6 ++-
 drivers/gpu/drm/i915/i915_pci.c          |  3 +-
 drivers/gpu/drm/i915/i915_reg.h          |  2 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 8 files changed, 60 insertions(+), 3 deletions(-)

Comments

Lis, Tomasz July 26, 2019, 6:49 p.m. UTC | #1 
On 2019-07-26 02:12, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
>
> Until Icelake, each engine had its own set of 64 MOCS registers. In
> order to simplify, Tigerlake moves to only 64 Global MOCS registers,
> which are no longer part of the engine context. Since these registers
> are now global, they also only need to be initialized once.
>
>  From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU
> management (5:4) fields and cannot be programmed to 'use the value from
> Private PAT', because these fields are no longer part of the PPAT. Also
> cacheability control (1:0) field has changed, 00 no longer means 'use
> controls from page table', but uncacheable (UC).
>
> v2: Move the changes to the fault registers to a separate commit - the old ones
>      overlap with the range used by the new global MOCS (requested by
>      Daniele)
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_mocs.c     | 47 ++++++++++++++++++++++++
>   drivers/gpu/drm/i915/gt/intel_mocs.h     |  1 +
>   drivers/gpu/drm/i915/i915_drv.h          |  2 +
>   drivers/gpu/drm/i915/i915_gem.c          |  1 +
>   drivers/gpu/drm/i915/i915_gpu_error.c    |  6 ++-
>   drivers/gpu/drm/i915/i915_pci.c          |  3 +-
>   drivers/gpu/drm/i915/i915_reg.h          |  2 +
>   drivers/gpu/drm/i915/intel_device_info.h |  1 +
>   8 files changed, 60 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index ca370c7487f9..9399c0ec08f1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -377,6 +377,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>   	unsigned int index;
>   	u32 unused_value;
>   
> +	/* Platforms with global MOCS do not need per-engine initialization. */
> +	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> +		return;
> +
>   	/* Called under a blanket forcewake */
>   	assert_forcewakes_active(uncore, FORCEWAKE_ALL);
>   
> @@ -401,6 +405,46 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>   				      unused_value);
>   }
>   
> +/**
> + * intel_mocs_init_global() - program the global mocs registers
> + * gt:      pointer to struct intel_gt
> + *
> + * This function initializes the MOCS global registers.
> + */
> +void intel_mocs_init_global(struct intel_gt *gt)
> +{
> +	struct intel_uncore *uncore = gt->uncore;
> +	struct drm_i915_mocs_table table;
> +	unsigned int index;
> +
> +	if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> +		return;
> +
> +	if (!get_mocs_settings(gt, &table))
> +		return;
> +
> +	if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
> +		return;
> +
> +	for (index = 0; index < table.size; index++)
> +		intel_uncore_write(uncore,
> +				   GEN12_GLOBAL_MOCS(index),
> +				   table.table[index].control_value);
> +
> +	/*
> +	 * Ok, now set the unused entries to uncached. These entries
> +	 * are officially undefined and no contract for the contents
> +	 * and settings is given for these entries.
> +	 *
> +	 * Entry 0 in the table is uncached - so we are just writing
> +	 * that value to all the used entries.
> +	 */
> +	for (; index < table.n_entries; index++)
> +		intel_uncore_write(uncore,
> +				   GEN12_GLOBAL_MOCS(index),
> +				   table.table[0].control_value);
While get_mocs_settings() can return a table with less than 64 entries, 
it will never be the case for platforms supporting global MOCS.
So this for() is actually a dead code.. but removing it could cause harm 
in case this is forgotten and modifications are made, so I'd leave it as is.

R-b: Tomasz Lis <tomasz.lis@intel.com>

-Tomasz
> +}
> +
>   /**
>    * emit_mocs_control_table() - emit the mocs control table
>    * @rq:	Request to set up the MOCS table for.
> @@ -604,6 +648,9 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
>   	struct drm_i915_mocs_table t;
>   	int ret;
>   
> +	if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
> +		return 0;
> +
>   	if (get_mocs_settings(rq->engine->gt, &t)) {
>   		/* Program the RCS control registers */
>   		ret = emit_mocs_control_table(rq, &t);
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
> index 8b9813e6f9ac..aa3a2df07c82 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> @@ -56,6 +56,7 @@ struct intel_gt;
>   
>   int intel_rcs_context_init_mocs(struct i915_request *rq);
>   void intel_mocs_init_l3cc_table(struct intel_gt *gt);
> +void intel_mocs_init_global(struct intel_gt *gt);
>   void intel_mocs_init_engine(struct intel_engine_cs *engine);
>   
>   #endif
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 59d4a1146039..a9509bdeb2fa 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2280,6 +2280,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   
>   #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
>   
> +#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
> +
>   #define INTEL_PCH_DEVICE_ID_MASK		0xff80
>   #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
>   #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 01dd0d1d9bf6..323218854b94 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1252,6 +1252,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
>   		goto out;
>   	}
>   
> +	intel_mocs_init_global(gt);
>   	intel_mocs_init_l3cc_table(gt);
>   
>   	intel_engines_set_scheduler_caps(i915);
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 41a14f40a8c7..146be1ce5ab8 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1524,8 +1524,10 @@ static void capture_reg_state(struct i915_gpu_state *error)
>   
>   	if (INTEL_GEN(i915) >= 6) {
>   		error->derrmr = intel_uncore_read(uncore, DERRMR);
> -		error->error = intel_uncore_read(uncore, ERROR_GEN6);
> -		error->done_reg = intel_uncore_read(uncore, DONE_REG);
> +		if (INTEL_GEN(i915) < 12) {
> +			error->error = intel_uncore_read(uncore, ERROR_GEN6);
> +			error->done_reg = intel_uncore_read(uncore, DONE_REG);
> +		}
>   	}
>   
>   	if (INTEL_GEN(i915) >= 5)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bd9211b3d76e..a7e1cde4a6d9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -783,7 +783,8 @@ static const struct intel_device_info intel_elkhartlake_info = {
>   		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
>   		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
>   		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> -	}
> +	}, \
> +	.has_global_mocs = 1
>   
>   static const struct intel_device_info intel_tigerlake_12_info = {
>   	GEN12_FEATURES,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 19e72f0c73d8..3bb83e14661c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11210,6 +11210,8 @@ enum skl_power_gate {
>   #define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
>   #define   PMFLUSHDONE_LNEBLK		(1 << 22)
>   
> +#define GEN12_GLOBAL_MOCS(i)	_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
> +
>   /* gamt regs */
>   #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
>   #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 4f58e8d71b67..92e0c2e0954c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -112,6 +112,7 @@ enum intel_ppgtt_type {
>   	func(gpu_reset_clobbers_display); \
>   	func(has_reset_engine); \
>   	func(has_fpga_dbg); \
> +	func(has_global_mocs); \
>   	func(has_gt_uc); \
>   	func(has_l3_dpf); \
>   	func(has_llc); \
Daniele Ceraolo Spurio July 26, 2019, 6:51 p.m. UTC | #2 
On 7/25/19 5:12 PM, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Until Icelake, each engine had its own set of 64 MOCS registers. In
> order to simplify, Tigerlake moves to only 64 Global MOCS registers,
> which are no longer part of the engine context. Since these registers
> are now global, they also only need to be initialized once.
> 
>  From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU
> management (5:4) fields and cannot be programmed to 'use the value from
> Private PAT', because these fields are no longer part of the PPAT. Also
> cacheability control (1:0) field has changed, 00 no longer means 'use
> controls from page table', but uncacheable (UC).
> 
> v2: Move the changes to the fault registers to a separate commit - the old ones
>      overlap with the range used by the new global MOCS (requested by
>      Daniele)
> 
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_mocs.c     | 47 ++++++++++++++++++++++++
>   drivers/gpu/drm/i915/gt/intel_mocs.h     |  1 +
>   drivers/gpu/drm/i915/i915_drv.h          |  2 +
>   drivers/gpu/drm/i915/i915_gem.c          |  1 +
>   drivers/gpu/drm/i915/i915_gpu_error.c    |  6 ++-
>   drivers/gpu/drm/i915/i915_pci.c          |  3 +-
>   drivers/gpu/drm/i915/i915_reg.h          |  2 +
>   drivers/gpu/drm/i915/intel_device_info.h |  1 +
>   8 files changed, 60 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index ca370c7487f9..9399c0ec08f1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -377,6 +377,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>   	unsigned int index;
>   	u32 unused_value;
>   
> +	/* Platforms with global MOCS do not need per-engine initialization. */
> +	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> +		return;
> +
>   	/* Called under a blanket forcewake */
>   	assert_forcewakes_active(uncore, FORCEWAKE_ALL);
>   
> @@ -401,6 +405,46 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>   				      unused_value);
>   }
>   
> +/**
> + * intel_mocs_init_global() - program the global mocs registers
> + * gt:      pointer to struct intel_gt
> + *
> + * This function initializes the MOCS global registers.
> + */
> +void intel_mocs_init_global(struct intel_gt *gt)
> +{
> +	struct intel_uncore *uncore = gt->uncore;
> +	struct drm_i915_mocs_table table;
> +	unsigned int index;
> +
> +	if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> +		return;
> +
> +	if (!get_mocs_settings(gt, &table))
> +		return;
> +
> +	if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
> +		return;
> +
> +	for (index = 0; index < table.size; index++)
> +		intel_uncore_write(uncore,
> +				   GEN12_GLOBAL_MOCS(index),
> +				   table.table[index].control_value);
> +
> +	/*
> +	 * Ok, now set the unused entries to uncached. These entries
> +	 * are officially undefined and no contract for the contents
> +	 * and settings is given for these entries.
> +	 *
> +	 * Entry 0 in the table is uncached - so we are just writing
> +	 * that value to all the used entries.
> +	 */
> +	for (; index < table.n_entries; index++)
> +		intel_uncore_write(uncore,
> +				   GEN12_GLOBAL_MOCS(index),
> +				   table.table[0].control_value) > +}

If we end up setting entry 0 to zero then the value here we should 
probably use a different entry (or just say we're setting everything to 
the invalid entry).

> +
>   /**
>    * emit_mocs_control_table() - emit the mocs control table
>    * @rq:	Request to set up the MOCS table for.
> @@ -604,6 +648,9 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
>   	struct drm_i915_mocs_table t;
>   	int ret;
>   
> +	if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
> +		return 0;
> +
>   	if (get_mocs_settings(rq->engine->gt, &t)) {
>   		/* Program the RCS control registers */
>   		ret = emit_mocs_control_table(rq, &t);
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
> index 8b9813e6f9ac..aa3a2df07c82 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> @@ -56,6 +56,7 @@ struct intel_gt;
>   
>   int intel_rcs_context_init_mocs(struct i915_request *rq);
>   void intel_mocs_init_l3cc_table(struct intel_gt *gt);
> +void intel_mocs_init_global(struct intel_gt *gt);
>   void intel_mocs_init_engine(struct intel_engine_cs *engine);
>   
>   #endif
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 59d4a1146039..a9509bdeb2fa 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2280,6 +2280,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   
>   #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
>   
> +#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
> +
>   #define INTEL_PCH_DEVICE_ID_MASK		0xff80
>   #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
>   #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 01dd0d1d9bf6..323218854b94 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1252,6 +1252,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
>   		goto out;
>   	}
>   
> +	intel_mocs_init_global(gt);
>   	intel_mocs_init_l3cc_table(gt);
>   
>   	intel_engines_set_scheduler_caps(i915);
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 41a14f40a8c7..146be1ce5ab8 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1524,8 +1524,10 @@ static void capture_reg_state(struct i915_gpu_state *error)
>   
>   	if (INTEL_GEN(i915) >= 6) {
>   		error->derrmr = intel_uncore_read(uncore, DERRMR);
> -		error->error = intel_uncore_read(uncore, ERROR_GEN6);
> -		error->done_reg = intel_uncore_read(uncore, DONE_REG);
> +		if (INTEL_GEN(i915) < 12) {
> +			error->error = intel_uncore_read(uncore, ERROR_GEN6);
> +			error->done_reg = intel_uncore_read(uncore, DONE_REG);
> +		}

Apologies for missing this in the previous review, but this looks like 
it could be split out as well, with an explanation that the registers 
have been removed on gen12. We should probably also stop printing them 
in the error state.

Daniele

>   	}
>   
>   	if (INTEL_GEN(i915) >= 5)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bd9211b3d76e..a7e1cde4a6d9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -783,7 +783,8 @@ static const struct intel_device_info intel_elkhartlake_info = {
>   		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
>   		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
>   		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> -	}
> +	}, \
> +	.has_global_mocs = 1
>   
>   static const struct intel_device_info intel_tigerlake_12_info = {
>   	GEN12_FEATURES,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 19e72f0c73d8..3bb83e14661c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11210,6 +11210,8 @@ enum skl_power_gate {
>   #define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
>   #define   PMFLUSHDONE_LNEBLK		(1 << 22)
>   
> +#define GEN12_GLOBAL_MOCS(i)	_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
> +
>   /* gamt regs */
>   #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
>   #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 4f58e8d71b67..92e0c2e0954c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -112,6 +112,7 @@ enum intel_ppgtt_type {
>   	func(gpu_reset_clobbers_display); \
>   	func(has_reset_engine); \
>   	func(has_fpga_dbg); \
> +	func(has_global_mocs); \
>   	func(has_gt_uc); \
>   	func(has_l3_dpf); \
>   	func(has_llc); \
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index ca370c7487f9..9399c0ec08f1 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -377,6 +377,10 @@  void intel_mocs_init_engine(struct intel_engine_cs *engine)
 	unsigned int index;
 	u32 unused_value;
 
+	/* Platforms with global MOCS do not need per-engine initialization. */
+	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+		return;
+
 	/* Called under a blanket forcewake */
 	assert_forcewakes_active(uncore, FORCEWAKE_ALL);
 
@@ -401,6 +405,46 @@  void intel_mocs_init_engine(struct intel_engine_cs *engine)
 				      unused_value);
 }
 
+/**
+ * intel_mocs_init_global() - program the global mocs registers
+ * gt:      pointer to struct intel_gt
+ *
+ * This function initializes the MOCS global registers.
+ */
+void intel_mocs_init_global(struct intel_gt *gt)
+{
+	struct intel_uncore *uncore = gt->uncore;
+	struct drm_i915_mocs_table table;
+	unsigned int index;
+
+	if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+		return;
+
+	if (!get_mocs_settings(gt, &table))
+		return;
+
+	if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
+		return;
+
+	for (index = 0; index < table.size; index++)
+		intel_uncore_write(uncore,
+				   GEN12_GLOBAL_MOCS(index),
+				   table.table[index].control_value);
+
+	/*
+	 * Ok, now set the unused entries to uncached. These entries
+	 * are officially undefined and no contract for the contents
+	 * and settings is given for these entries.
+	 *
+	 * Entry 0 in the table is uncached - so we are just writing
+	 * that value to all the used entries.
+	 */
+	for (; index < table.n_entries; index++)
+		intel_uncore_write(uncore,
+				   GEN12_GLOBAL_MOCS(index),
+				   table.table[0].control_value);
+}
+
 /**
  * emit_mocs_control_table() - emit the mocs control table
  * @rq:	Request to set up the MOCS table for.
@@ -604,6 +648,9 @@  int intel_rcs_context_init_mocs(struct i915_request *rq)
 	struct drm_i915_mocs_table t;
 	int ret;
 
+	if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
+		return 0;
+
 	if (get_mocs_settings(rq->engine->gt, &t)) {
 		/* Program the RCS control registers */
 		ret = emit_mocs_control_table(rq, &t);
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index 8b9813e6f9ac..aa3a2df07c82 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -56,6 +56,7 @@  struct intel_gt;
 
 int intel_rcs_context_init_mocs(struct i915_request *rq);
 void intel_mocs_init_l3cc_table(struct intel_gt *gt);
+void intel_mocs_init_global(struct intel_gt *gt);
 void intel_mocs_init_engine(struct intel_engine_cs *engine);
 
 #endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 59d4a1146039..a9509bdeb2fa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2280,6 +2280,8 @@  IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
 
+#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
+
 #define INTEL_PCH_DEVICE_ID_MASK		0xff80
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 01dd0d1d9bf6..323218854b94 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1252,6 +1252,7 @@  int i915_gem_init_hw(struct drm_i915_private *i915)
 		goto out;
 	}
 
+	intel_mocs_init_global(gt);
 	intel_mocs_init_l3cc_table(gt);
 
 	intel_engines_set_scheduler_caps(i915);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 41a14f40a8c7..146be1ce5ab8 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1524,8 +1524,10 @@  static void capture_reg_state(struct i915_gpu_state *error)
 
 	if (INTEL_GEN(i915) >= 6) {
 		error->derrmr = intel_uncore_read(uncore, DERRMR);
-		error->error = intel_uncore_read(uncore, ERROR_GEN6);
-		error->done_reg = intel_uncore_read(uncore, DONE_REG);
+		if (INTEL_GEN(i915) < 12) {
+			error->error = intel_uncore_read(uncore, ERROR_GEN6);
+			error->done_reg = intel_uncore_read(uncore, DONE_REG);
+		}
 	}
 
 	if (INTEL_GEN(i915) >= 5)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bd9211b3d76e..a7e1cde4a6d9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -783,7 +783,8 @@  static const struct intel_device_info intel_elkhartlake_info = {
 		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
-	}
+	}, \
+	.has_global_mocs = 1
 
 static const struct intel_device_info intel_tigerlake_12_info = {
 	GEN12_FEATURES,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 19e72f0c73d8..3bb83e14661c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11210,6 +11210,8 @@  enum skl_power_gate {
 #define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
 #define   PMFLUSHDONE_LNEBLK		(1 << 22)
 
+#define GEN12_GLOBAL_MOCS(i)	_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4f58e8d71b67..92e0c2e0954c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -112,6 +112,7 @@  enum intel_ppgtt_type {
 	func(gpu_reset_clobbers_display); \
 	func(has_reset_engine); \
 	func(has_fpga_dbg); \
+	func(has_global_mocs); \
 	func(has_gt_uc); \
 	func(has_l3_dpf); \
 	func(has_llc); \