Message ID | 20190726002412.5827-2-lucas.demarchi@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Tiger Lake: register moves | expand |
On 7/26/2019 5:54 AM, Lucas De Marchi wrote: > From: José Roberto de Souza <jose.souza@intel.com> > > Tiger Lake has a new register offset for DC5 and DC6 residency counters. > > v2: > - Rename registers since they are not in the CSR memory range > (requested by Anshuman) > - Fix type (requested by Matthew) > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Looks Good to me. Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++-------- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 2 files changed, 15 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 24787bb48c9f..6dbd85b38759 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) > struct drm_i915_private *dev_priv = node_to_i915(m->private); > intel_wakeref_t wakeref; > struct intel_csr *csr; > + i915_reg_t dc5_reg, dc6_reg = {}; > > if (!HAS_CSR(dev_priv)) > return -ENODEV; > @@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused) > seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), > CSR_VERSION_MINOR(csr->version)); > > - if (WARN_ON(INTEL_GEN(dev_priv) > 11)) > - goto out; > + if (INTEL_GEN(dev_priv) >= 12) { > + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; > + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; > + } else { > + dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : > + SKL_CSR_DC3_DC5_COUNT; > + if (!IS_GEN9_LP(dev_priv)) > + dc6_reg = SKL_CSR_DC5_DC6_COUNT; > + } > > - seq_printf(m, "DC3 -> DC5 count: %d\n", > - I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : > - SKL_CSR_DC3_DC5_COUNT)); > - if (!IS_GEN9_LP(dev_priv)) > - seq_printf(m, "DC5 -> DC6 count: %d\n", > - I915_READ(SKL_CSR_DC5_DC6_COUNT)); > + seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg)); > + if (dc6_reg.reg) > + seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg)); > > out: > seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 24f2a52a2b42..e999ce94b45c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7268,6 +7268,8 @@ enum { > #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) > #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) > #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) > +#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) > +#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) > > /* interrupts */ > #define DE_MASTER_IRQ_CONTROL (1 << 31) >
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 24787bb48c9f..6dbd85b38759 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) struct drm_i915_private *dev_priv = node_to_i915(m->private); intel_wakeref_t wakeref; struct intel_csr *csr; + i915_reg_t dc5_reg, dc6_reg = {}; if (!HAS_CSR(dev_priv)) return -ENODEV; @@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused) seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), CSR_VERSION_MINOR(csr->version)); - if (WARN_ON(INTEL_GEN(dev_priv) > 11)) - goto out; + if (INTEL_GEN(dev_priv) >= 12) { + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; + } else { + dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : + SKL_CSR_DC3_DC5_COUNT; + if (!IS_GEN9_LP(dev_priv)) + dc6_reg = SKL_CSR_DC5_DC6_COUNT; + } - seq_printf(m, "DC3 -> DC5 count: %d\n", - I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : - SKL_CSR_DC3_DC5_COUNT)); - if (!IS_GEN9_LP(dev_priv)) - seq_printf(m, "DC5 -> DC6 count: %d\n", - I915_READ(SKL_CSR_DC5_DC6_COUNT)); + seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg)); + if (dc6_reg.reg) + seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg)); out: seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 24f2a52a2b42..e999ce94b45c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7268,6 +7268,8 @@ enum { #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) +#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) +#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) /* interrupts */ #define DE_MASTER_IRQ_CONTROL (1 << 31)