diff mbox series

[3/3] drm/i915/tgl: add support for reading the timestamp frequency

Message ID 20190726002412.5827-4-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Tiger Lake: register moves | expand

Commit Message

Lucas De Marchi July 26, 2019, 12:24 a.m. UTC 
From: Michel Thierry <michel.thierry@intel.com>

There are no changes with respect to GEN11, which Paulo wrote.

This gets rid of the "Missing switch case in read_timestamp_frequency"
message at boot for Tiger Lake.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..a3017d16b7f3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -716,7 +716,7 @@  static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		}
 
 		return freq;
-	} else if (INTEL_GEN(dev_priv) <= 11) {
+	} else if (INTEL_GEN(dev_priv) <= 12) {
 		u32 ctc_reg = I915_READ(CTC_MODE);
 		u32 freq = 0;