diff mbox series

[06/39] drm/i915/bdw+: Enable PSR in any eDP port

Message ID 20190816080503.28594-7-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Tiger Lake batch 3 | expand

Commit Message

Lucas De Marchi Aug. 16, 2019, 8:04 a.m. UTC
From: José Roberto de Souza <jose.souza@intel.com>

From BDW+ the PSR registers moved from DDIA to transcoder, so any port
with a eDP panel connected can have PSR, so lets remove this limitation.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

Comments

Gupta, Anshuman Aug. 22, 2019, 4:20 p.m. UTC | #1
Verified from B.Specs:7723 and B.Spec:8041

On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
>  From BDW+ the PSR registers moved from DDIA to transcoder, so any port
> with a eDP panel connected can have PSR, so lets remove this limitation.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
>   1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 36bdc16fb43b..6eedd8281e72 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -578,11 +578,10 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>   
>   	/*
>   	 * HSW spec explicitly says PSR is tied to port A.
> -	 * BDW+ platforms have a instance of PSR registers per transcoder but
> -	 * for now it only supports one instance of PSR, so lets keep it
> -	 * hardcoded to PORT_A
> +         * BDW+ platforms with DDI implementation of PSR have different
> +	 * PSR registers per transcoder.
>   	 */
> -	if (dig_port->base.port != PORT_A) {
> +	if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
>   		DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
>   		return;
>   	}
>
Gupta, Anshuman Aug. 22, 2019, 4:42 p.m. UTC | #2
On 8/22/2019 9:50 PM, Gupta, Anshuman wrote:
> Verified from B.Specs:7723 and B.Spec:8041
> 
> On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
>> From: José Roberto de Souza <jose.souza@intel.com>
>>
>>  From BDW+ the PSR registers moved from DDIA to transcoder, so any port
>> with a eDP panel connected can have PSR, so lets remove this limitation.
>>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
>>   1 file changed, 3 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 36bdc16fb43b..6eedd8281e72 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -578,11 +578,10 @@ void intel_psr_compute_config(struct intel_dp 
>> *intel_dp,
>>       /*
>>        * HSW spec explicitly says PSR is tied to port A.
>> -     * BDW+ platforms have a instance of PSR registers per transcoder 
>> but
>> -     * for now it only supports one instance of PSR, so lets keep it
>> -     * hardcoded to PORT_A
>> +         * BDW+ platforms with DDI implementation of PSR have different
>> +     * PSR registers per transcoder.
>>        */
>> -    if (dig_port->base.port != PORT_A) {
>> +    if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
>>           DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
>>           return;
>>       }
>>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 36bdc16fb43b..6eedd8281e72 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -578,11 +578,10 @@  void intel_psr_compute_config(struct intel_dp *intel_dp,
 
 	/*
 	 * HSW spec explicitly says PSR is tied to port A.
-	 * BDW+ platforms have a instance of PSR registers per transcoder but
-	 * for now it only supports one instance of PSR, so lets keep it
-	 * hardcoded to PORT_A
+         * BDW+ platforms with DDI implementation of PSR have different
+	 * PSR registers per transcoder.
 	 */
-	if (dig_port->base.port != PORT_A) {
+	if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
 		DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
 		return;
 	}