diff mbox series

[v2,09/14] drm/i915/fbc: s/gen9 && !glk/gen9_bc || bxt/

Message ID 20191127201222.16669-10-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/fbc: Fix FBC for glk+ | expand

Commit Message

Ville Syrjälä Nov. 27, 2019, 8:12 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the 'gen9 && !glk' with the slightly more obvious
'gen9_bc || bxt'.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index c25e9ecb8506..9a57ebc16c74 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -281,7 +281,7 @@  static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 	int threshold = dev_priv->fbc.threshold;
 
 	/* Display WA #0529: skl, kbl, bxt. */
-	if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
 		u32 val = I915_READ(CHICKEN_MISC_4);
 
 		val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
@@ -1089,7 +1089,7 @@  void intel_fbc_enable(struct intel_crtc *crtc,
 		goto out;
 	}
 
-	if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) &&
+	if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) &&
 	    fb->modifier != I915_FORMAT_MOD_X_TILED)
 		cache->gen9_wa_cfb_stride =
 			DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;