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[RFC,41/60] drm/i915: Distinction of memory regions

Message ID 20200710115757.290984-42-matthew.auld@intel.com (mailing list archive)
State New, archived
Headers show
Series DG1 LMEM enabling | expand

Commit Message

Matthew Auld July 10, 2020, 11:57 a.m. UTC 
From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

IGTs should be able to choose testing strategy depending on memory
regions and its sizes. Add region instance number to make this
easier and descriptive.

Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Adam Miszczak <adam.miszczak@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 drivers/gpu/drm/i915/intel_memory_region.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index b4b7858f13e0..eeea520f97ba 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -313,6 +313,10 @@  int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
 		mem->type = type;
 		mem->instance = instance;
 
+		if (HAS_LMEM(mem->i915) && type != INTEL_MEMORY_SYSTEM)
+			intel_memory_region_set_name(mem, "%s%u",
+						     mem->name, mem->instance);
+
 		i915->mm.regions[i] = mem;
 	}