@@ -12038,6 +12038,8 @@ enum skl_power_gate {
#define GEN12_LMEM_CFG_ADDR _MMIO(0xcf58)
#define LMEM_ENABLE (1 << 31)
+#define GEN12_GSMBASE _MMIO(0x108100)
+
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
@@ -44,20 +44,23 @@ const struct intel_memory_region_ops intel_region_lmem_ops = {
static struct intel_memory_region *
setup_lmem(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
struct pci_dev *pdev = dev_priv->drm.pdev;
struct intel_memory_region *mem;
resource_size_t io_start;
- resource_size_t size;
+ resource_size_t lmem_size;
/* Enables Local Memory functionality in GAM */
I915_WRITE(GEN12_LMEM_CFG_ADDR, I915_READ(GEN12_LMEM_CFG_ADDR) | LMEM_ENABLE);
+ /* Stolen starts from GSMBASE on DG1 */
+ lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE);
+
io_start = pci_resource_start(pdev, 2);
- size = pci_resource_len(pdev, 2);
mem = intel_memory_region_create(dev_priv,
0,
- size,
+ lmem_size,
I915_GTT_PAGE_SIZE_4K,
io_start,
&intel_region_lmem_ops);
@@ -66,7 +69,7 @@ setup_lmem(struct drm_i915_private *dev_priv)
DRM_INFO("Intel graphics LMEM IO start: %llx\n",
(u64)mem->io_start);
DRM_INFO("Intel graphics LMEM size: %llx\n",
- (u64)size);
+ (u64)lmem_size);
}
return mem;