| Message ID | 20201111162408.98002-2-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915/display: Group DC9 mask set | expand |
On Wed, Nov 11, 2020 at 08:24:08AM -0800, Jose Souza wrote: >Just following what we do in many other places, DG1 is a exception so >move it to the top instead of add it inside of INTEL_GEN(dev_priv) >= 12. > >Cc: Lucas De Marchi <lucas.demarchi@intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi >--- > .../gpu/drm/i915/display/intel_display_power.c | 18 +++++++----------- > 1 file changed, 7 insertions(+), 11 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c >index 48d41a43fbb2..31cb9ac5c489 100644 >--- a/drivers/gpu/drm/i915/display/intel_display_power.c >+++ b/drivers/gpu/drm/i915/display/intel_display_power.c >@@ -4492,20 +4492,16 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, > int requested_dc; > int max_dc; > >- if (INTEL_GEN(dev_priv) >= 12) { >- if (IS_DG1(dev_priv)) >- max_dc = 3; >- else >- max_dc = 4; >- } else if (IS_GEN(dev_priv, 11)) { >+ if (IS_DG1(dev_priv)) >+ max_dc = 3; >+ else if (INTEL_GEN(dev_priv) >= 12) >+ max_dc = 4; >+ else if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_BC(dev_priv)) > max_dc = 2; >- } else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) { >- max_dc = 2; >- } else if (IS_GEN9_LP(dev_priv)) { >+ else if (IS_GEN9_LP(dev_priv)) > max_dc = 1; >- } else { >+ else > max_dc = 0; >- } > > /* > * DC9 has a separate HW flow from the rest of the DC states, >-- >2.29.2 >
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 48d41a43fbb2..31cb9ac5c489 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4492,20 +4492,16 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, int requested_dc; int max_dc; - if (INTEL_GEN(dev_priv) >= 12) { - if (IS_DG1(dev_priv)) - max_dc = 3; - else - max_dc = 4; - } else if (IS_GEN(dev_priv, 11)) { + if (IS_DG1(dev_priv)) + max_dc = 3; + else if (INTEL_GEN(dev_priv) >= 12) + max_dc = 4; + else if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_BC(dev_priv)) max_dc = 2; - } else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) { - max_dc = 2; - } else if (IS_GEN9_LP(dev_priv)) { + else if (IS_GEN9_LP(dev_priv)) max_dc = 1; - } else { + else max_dc = 0; - } /* * DC9 has a separate HW flow from the rest of the DC states,
Just following what we do in many other places, DG1 is a exception so move it to the top instead of add it inside of INTEL_GEN(dev_priv) >= 12. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- .../gpu/drm/i915/display/intel_display_power.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-)