diff mbox series

[RFC,127/162] drm/i915: Allow non-uniform subslices in gen12+

Message ID 20201127120718.454037-128-matthew.auld@intel.com (mailing list archive)
State New, archived
Headers show
Series DG1 + LMEM enabling | expand

Commit Message

Matthew Auld Nov. 27, 2020, 12:06 p.m. UTC 
From: Stuart Summers <stuart.summers@intel.com>

The current implementation of intel_set_subslices only takes
the number of bits per subslice stride and copies those in
based on the slice given. For all known use cases, this works
fine. But in the event of some faulty hardware or other future
use case, do a straight memcpy of these subslice bits into
the internal mask to ensure all subslices are correctly
calculated.

Cc: Harish Chegondi <harish.chegondi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Suggested-by: Harish Chegondi <harish.chegondi@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 8a72e0fe34ca..b8a945166d32 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -104,6 +104,7 @@  static u16 compute_eu_total(const struct sseu_dev_info *sseu)
 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
 				    u8 s_en, u32 ss_en, u16 eu_en)
 {
+	u32 ss_mask;
 	int s, ss;
 
 	/* ss_en represents entire subslice mask across all slices */
@@ -116,7 +117,10 @@  static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
 
 		sseu->slice_mask |= BIT(s);
 
-		intel_sseu_set_subslices(sseu, s, ss_en);
+		ss_mask = ss_en >> (s * sseu->max_subslices);
+		ss_mask &= GENMASK(sseu->max_subslices - 1, 0);
+
+		intel_sseu_set_subslices(sseu, s, ss_mask);
 
 		for (ss = 0; ss < sseu->max_subslices; ss++)
 			if (intel_sseu_has_subslice(sseu, s, ss))