diff mbox series

[01/18] drm/i915/display13: add Display13 characteristics

Message ID 20210128192413.1715802-2-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series Preliminary Display13 support | expand

Commit Message

Matt Roper Jan. 28, 2021, 7:23 p.m. UTC 
Let's start preparing for upcoming platforms that will use a Display13
design.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  1 +
 drivers/gpu/drm/i915/i915_pci.c          | 11 +++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  2 ++
 3 files changed, 14 insertions(+)

Comments

Lucas De Marchi Feb. 11, 2021, 12:03 a.m. UTC | #1 
On Thu, Jan 28, 2021 at 11:23:56AM -0800, Matt Roper wrote:
>Let's start preparing for upcoming platforms that will use a Display13
>design.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.h          |  1 +
> drivers/gpu/drm/i915/i915_pci.c          | 11 +++++++++++
> drivers/gpu/drm/i915/intel_device_info.h |  2 ++
> 3 files changed, 14 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 9713ab963122..1c0fdbf800ac 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1778,6 +1778,7 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
> #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
>
> #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
>+#define HAS_DISPLAY13(dev_priv) (INTEL_INFO(dev_priv)->has_display13)
>
> #define HAS_VRR(i915)	(INTEL_GEN(i915) >= 12)
>
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index 6cff7cf0f17b..e5e10484bf8d 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -936,6 +936,17 @@ static const struct intel_device_info adl_s_info = {
> 	.dma_mask_size = 46,
> };
>
>+#define DISPLAY13_FEATURES \
>+	.has_display13 = 1,						\
>+	.display.has_psr_hw_tracking = 0,				\
>+	.abox_mask = GENMASK(1, 0),					\
>+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
>+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |	\
>+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),			\
>+	.ddb_size = 4096,						\
>+	.mbus_size = 2048,						\
>+	.num_supported_dbuf_slices = 4,
>+
> #undef GEN
> #undef PLATFORM
>
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index e6ca1023ffcf..ba44c2c10ad8 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -116,6 +116,7 @@ enum intel_ppgtt_type {
> 	func(is_dgfx); \
> 	/* Keep has_* in alphabetical order */ \
> 	func(has_64bit_reloc); \
>+	func(has_display13); \

shouldn't this be inside display struct?

> 	func(gpu_reset_clobbers_display); \
> 	func(has_reset_engine); \
> 	func(has_fpga_dbg); \
>@@ -193,6 +194,7 @@ struct intel_device_info {
> 	} display;
>
> 	u16 ddb_size; /* in blocks */
>+	u16 mbus_size; /* total ddb size on one mbus */

this is unused and afaics never will. It'd be better if if this is
introduced only together with the feature.

Lucas De Marchi

> 	u8 num_supported_dbuf_slices; /* number of DBuf slices */
>
> 	/* Register offsets for the various display pipes and transcoders */
>-- 
>2.25.4
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9713ab963122..1c0fdbf800ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1778,6 +1778,7 @@  tgl_stepping_get(struct drm_i915_private *dev_priv)
 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
 
 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
+#define HAS_DISPLAY13(dev_priv) (INTEL_INFO(dev_priv)->has_display13)
 
 #define HAS_VRR(i915)	(INTEL_GEN(i915) >= 12)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6cff7cf0f17b..e5e10484bf8d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -936,6 +936,17 @@  static const struct intel_device_info adl_s_info = {
 	.dma_mask_size = 46,
 };
 
+#define DISPLAY13_FEATURES \
+	.has_display13 = 1,						\
+	.display.has_psr_hw_tracking = 0,				\
+	.abox_mask = GENMASK(1, 0),					\
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |	\
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),			\
+	.ddb_size = 4096,						\
+	.mbus_size = 2048,						\
+	.num_supported_dbuf_slices = 4,
+
 #undef GEN
 #undef PLATFORM
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e6ca1023ffcf..ba44c2c10ad8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -116,6 +116,7 @@  enum intel_ppgtt_type {
 	func(is_dgfx); \
 	/* Keep has_* in alphabetical order */ \
 	func(has_64bit_reloc); \
+	func(has_display13); \
 	func(gpu_reset_clobbers_display); \
 	func(has_reset_engine); \
 	func(has_fpga_dbg); \
@@ -193,6 +194,7 @@  struct intel_device_info {
 	} display;
 
 	u16 ddb_size; /* in blocks */
+	u16 mbus_size; /* total ddb size on one mbus */
 	u8 num_supported_dbuf_slices; /* number of DBuf slices */
 
 	/* Register offsets for the various display pipes and transcoders */