| Message ID | 20211006204937.30774-6-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: DP per-lane drive settings for icl+ | expand |
On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > DKL_TX_LOADGEN_SHARING_PMD_DISABLE doesn't even seem to exist, > also the spec says to skip all loadgen stuff. > > The code was dead anyway since it wasn't actually writing the value > anywhere. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> I admit not looking this up in spec, but this is dead code removal anyway... Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 8 -------- > drivers/gpu/drm/i915/i915_reg.h | 1 - > 2 files changed, 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 0c9ed705af47..b8ec53d9e3b0 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1309,14 +1309,6 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, > val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); > val &= ~DKL_TX_DP20BITMODE; > intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); > - > - if ((intel_crtc_has_dp_encoder(crtc_state) && > - crtc_state->port_clock == 162000) || > - (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && > - crtc_state->port_clock == 594000)) > - val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE; > - else > - val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE; > } > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5e7a55e6ef50..8c8152de643f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -11022,7 +11022,6 @@ enum skl_power_gate { > _DKL_TX_DPCNTL1) > > #define _DKL_TX_DPCNTL2 0x2C8 > -#define DKL_TX_LOADGEN_SHARING_PMD_DISABLE REG_BIT(12) > #define DKL_TX_DP20BITMODE (1 << 2) > #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ > _DKL_PHY1_BASE, \
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 0c9ed705af47..b8ec53d9e3b0 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1309,14 +1309,6 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); val &= ~DKL_TX_DP20BITMODE; intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); - - if ((intel_crtc_has_dp_encoder(crtc_state) && - crtc_state->port_clock == 162000) || - (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && - crtc_state->port_clock == 594000)) - val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE; - else - val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE; } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5e7a55e6ef50..8c8152de643f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -11022,7 +11022,6 @@ enum skl_power_gate { _DKL_TX_DPCNTL1) #define _DKL_TX_DPCNTL2 0x2C8 -#define DKL_TX_LOADGEN_SHARING_PMD_DISABLE REG_BIT(12) #define DKL_TX_DP20BITMODE (1 << 2) #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ _DKL_PHY1_BASE, \