diff mbox series

[v2,04/13] drm/i915/xehp: compute engine pipe_control

Message ID 20220228174245.1569581-5-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series i915: Prepare for Xe_HP compute engines | expand

Commit Message

Matt Roper Feb. 28, 2022, 5:42 p.m. UTC 
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

CCS will reuse the RCS functions for breadcrumb and flush emission.
However, CCS pipe_control has additional programming restrictions:
 - Command Streamer Stall Enable must be always set
 - Post Sync Operations must not be set to Write PS Depth Count
 - 3D-related bits must not be set

Bspec: 47112
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c     | 35 +++++++++++++++-----
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 +++++++++
 2 files changed, 41 insertions(+), 9 deletions(-)

Comments

Lucas De Marchi March 1, 2022, 6:54 a.m. UTC | #1 
On Mon, Feb 28, 2022 at 09:42:36AM -0800, Matt Roper wrote:
>From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
>CCS will reuse the RCS functions for breadcrumb and flush emission.
>However, CCS pipe_control has additional programming restrictions:
> - Command Streamer Stall Enable must be always set
> - Post Sync Operations must not be set to Write PS Depth Count
> - 3D-related bits must not be set
>
>Bspec: 47112
>Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c     | 35 +++++++++++++++-----
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 +++++++++
> 2 files changed, 41 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>index 1f8cf4f790b2..0a29eaf8b0df 100644
>--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>@@ -201,6 +201,8 @@ static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
>
> int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> {
>+	struct intel_engine_cs *engine = rq->engine;
>+
> 	if (mode & EMIT_FLUSH) {
> 		u32 flags = 0;
> 		u32 *cs;
>@@ -219,6 +221,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
>
> 		flags |= PIPE_CONTROL_CS_STALL;
>
>+		if (engine->class == COMPUTE_CLASS)
>+			flags &= ~PIPE_CONTROL_3D_FLAGS;
>+
> 		cs = intel_ring_begin(rq, 6);
> 		if (IS_ERR(cs))
> 			return PTR_ERR(cs);
>@@ -246,6 +251,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
>
> 		flags |= PIPE_CONTROL_CS_STALL;
>
>+		if (engine->class == COMPUTE_CLASS)
>+			flags &= ~PIPE_CONTROL_3D_FLAGS;
>+
> 		cs = intel_ring_begin(rq, 8 + 4);
> 		if (IS_ERR(cs))
> 			return PTR_ERR(cs);
>@@ -618,19 +626,28 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
>
> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> {
>+	struct drm_i915_private *i915 = rq->engine->i915;
>+

extra blank line here


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>+	u32 flags = (PIPE_CONTROL_CS_STALL |
>+		     PIPE_CONTROL_TILE_CACHE_FLUSH |
>+		     PIPE_CONTROL_FLUSH_L3 |
>+		     PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
>+		     PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>+		     PIPE_CONTROL_DC_FLUSH_ENABLE |
>+		     PIPE_CONTROL_FLUSH_ENABLE);
>+
>+	if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
>+		/* Wa_1409600907 */
>+		flags |= PIPE_CONTROL_DEPTH_STALL;
>+
>+	if (rq->engine->class == COMPUTE_CLASS)
>+		flags &= ~PIPE_CONTROL_3D_FLAGS;
>+
> 	cs = gen12_emit_ggtt_write_rcs(cs,
> 				       rq->fence.seqno,
> 				       hwsp_offset(rq),
> 				       PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
>-				       PIPE_CONTROL_CS_STALL |
>-				       PIPE_CONTROL_TILE_CACHE_FLUSH |
>-				       PIPE_CONTROL_FLUSH_L3 |
>-				       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
>-				       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>-				       /* Wa_1409600907:tgl */
>-				       PIPE_CONTROL_DEPTH_STALL |
>-				       PIPE_CONTROL_DC_FLUSH_ENABLE |
>-				       PIPE_CONTROL_FLUSH_ENABLE);
>+				       flags);
>
> 	return gen12_emit_fini_breadcrumb_tail(rq, cs);
> }
>diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>index f8253012d166..d112ffd56418 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>@@ -228,11 +228,14 @@
> #define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
> #define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
> #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
>+#define   PIPE_CONTROL_AMFS_FLUSH			(1<<25) /* gen12+ */
> #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
> #define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
> #define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
> #define   PIPE_CONTROL_CS_STALL				(1<<20)
>+#define   PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET		(1<<19)
> #define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
>+#define   PIPE_CONTROL_PSD_SYNC				(1<<17) /* gen11+ */
> #define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
> #define   PIPE_CONTROL_WRITE_TIMESTAMP			(3<<14)
> #define   PIPE_CONTROL_QW_WRITE				(1<<14)
>@@ -254,6 +257,18 @@
> #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
> #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
>
>+/* 3D-related flags can't be set on compute engine */
>+#define PIPE_CONTROL_3D_FLAGS (\
>+		PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
>+		PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
>+		PIPE_CONTROL_TILE_CACHE_FLUSH | \
>+		PIPE_CONTROL_DEPTH_STALL | \
>+		PIPE_CONTROL_STALL_AT_SCOREBOARD | \
>+		PIPE_CONTROL_PSD_SYNC | \
>+		PIPE_CONTROL_AMFS_FLUSH | \
>+		PIPE_CONTROL_VF_CACHE_INVALIDATE | \
>+		PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
>+
> #define MI_MATH(x)			MI_INSTR(0x1a, (x) - 1)
> #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> /* Opcodes for MI_MATH_INSTR */
>-- 
>2.34.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 1f8cf4f790b2..0a29eaf8b0df 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -201,6 +201,8 @@  static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
 
 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 {
+	struct intel_engine_cs *engine = rq->engine;
+
 	if (mode & EMIT_FLUSH) {
 		u32 flags = 0;
 		u32 *cs;
@@ -219,6 +221,9 @@  int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 
 		flags |= PIPE_CONTROL_CS_STALL;
 
+		if (engine->class == COMPUTE_CLASS)
+			flags &= ~PIPE_CONTROL_3D_FLAGS;
+
 		cs = intel_ring_begin(rq, 6);
 		if (IS_ERR(cs))
 			return PTR_ERR(cs);
@@ -246,6 +251,9 @@  int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 
 		flags |= PIPE_CONTROL_CS_STALL;
 
+		if (engine->class == COMPUTE_CLASS)
+			flags &= ~PIPE_CONTROL_3D_FLAGS;
+
 		cs = intel_ring_begin(rq, 8 + 4);
 		if (IS_ERR(cs))
 			return PTR_ERR(cs);
@@ -618,19 +626,28 @@  u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
 
 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 {
+	struct drm_i915_private *i915 = rq->engine->i915;
+
+	u32 flags = (PIPE_CONTROL_CS_STALL |
+		     PIPE_CONTROL_TILE_CACHE_FLUSH |
+		     PIPE_CONTROL_FLUSH_L3 |
+		     PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+		     PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+		     PIPE_CONTROL_DC_FLUSH_ENABLE |
+		     PIPE_CONTROL_FLUSH_ENABLE);
+
+	if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+		/* Wa_1409600907 */
+		flags |= PIPE_CONTROL_DEPTH_STALL;
+
+	if (rq->engine->class == COMPUTE_CLASS)
+		flags &= ~PIPE_CONTROL_3D_FLAGS;
+
 	cs = gen12_emit_ggtt_write_rcs(cs,
 				       rq->fence.seqno,
 				       hwsp_offset(rq),
 				       PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
-				       PIPE_CONTROL_CS_STALL |
-				       PIPE_CONTROL_TILE_CACHE_FLUSH |
-				       PIPE_CONTROL_FLUSH_L3 |
-				       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
-				       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-				       /* Wa_1409600907:tgl */
-				       PIPE_CONTROL_DEPTH_STALL |
-				       PIPE_CONTROL_DC_FLUSH_ENABLE |
-				       PIPE_CONTROL_FLUSH_ENABLE);
+				       flags);
 
 	return gen12_emit_fini_breadcrumb_tail(rq, cs);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index f8253012d166..d112ffd56418 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -228,11 +228,14 @@ 
 #define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
 #define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
 #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
+#define   PIPE_CONTROL_AMFS_FLUSH			(1<<25) /* gen12+ */
 #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
 #define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
 #define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
 #define   PIPE_CONTROL_CS_STALL				(1<<20)
+#define   PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET		(1<<19)
 #define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
+#define   PIPE_CONTROL_PSD_SYNC				(1<<17) /* gen11+ */
 #define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
 #define   PIPE_CONTROL_WRITE_TIMESTAMP			(3<<14)
 #define   PIPE_CONTROL_QW_WRITE				(1<<14)
@@ -254,6 +257,18 @@ 
 #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
 #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
 
+/* 3D-related flags can't be set on compute engine */
+#define PIPE_CONTROL_3D_FLAGS (\
+		PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
+		PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
+		PIPE_CONTROL_TILE_CACHE_FLUSH | \
+		PIPE_CONTROL_DEPTH_STALL | \
+		PIPE_CONTROL_STALL_AT_SCOREBOARD | \
+		PIPE_CONTROL_PSD_SYNC | \
+		PIPE_CONTROL_AMFS_FLUSH | \
+		PIPE_CONTROL_VF_CACHE_INVALIDATE | \
+		PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
+
 #define MI_MATH(x)			MI_INSTR(0x1a, (x) - 1)
 #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
 /* Opcodes for MI_MATH_INSTR */