diff mbox series

[v2,06/13] drm/i915: Move context descriptor fields to intel_lrc.h

Message ID 20220228174245.1569581-7-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series i915: Prepare for Xe_HP compute engines | expand

Commit Message

Matt Roper Feb. 28, 2022, 5:42 p.m. UTC 
This is a more appropriate header for these definitions.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  1 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 34 -----------------------
 drivers/gpu/drm/i915/gt/intel_lrc.h       | 34 +++++++++++++++++++++++
 3 files changed, 35 insertions(+), 34 deletions(-)

Comments

Lucas De Marchi March 1, 2022, 6:57 a.m. UTC | #1 
On Mon, Feb 28, 2022 at 09:42:38AM -0800, Matt Roper wrote:
>This is a more appropriate header for these definitions.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c |  1 +
> drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 34 -----------------------
> drivers/gpu/drm/i915/gt/intel_lrc.h       | 34 +++++++++++++++++++++++
> 3 files changed, 35 insertions(+), 34 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>index edba18c942cf..b0982a9e4476 100644
>--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>@@ -21,6 +21,7 @@
> #include "intel_gt.h"
> #include "intel_gt_requests.h"
> #include "intel_gt_pm.h"
>+#include "intel_lrc.h"
> #include "intel_lrc_reg.h"
> #include "intel_reset.h"
> #include "intel_ring.h"
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>index 69b826a3c381..84f189738a68 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>@@ -1499,38 +1499,4 @@
>
> #define GEN12_SFC_DONE(n)			_MMIO(0x1cc000 + (n) * 0x1000)
>
>-enum {
>-	INTEL_ADVANCED_CONTEXT = 0,
>-	INTEL_LEGACY_32B_CONTEXT,
>-	INTEL_ADVANCED_AD_CONTEXT,
>-	INTEL_LEGACY_64B_CONTEXT
>-};
>-
>-enum {
>-	FAULT_AND_HANG = 0,
>-	FAULT_AND_HALT, /* Debug only */
>-	FAULT_AND_STREAM,
>-	FAULT_AND_CONTINUE /* Unsupported */
>-};
>-
>-#define   CTX_GTT_ADDRESS_MASK			GENMASK(31, 12)
>-#define   GEN8_CTX_VALID			(1 << 0)
>-#define   GEN8_CTX_FORCE_PD_RESTORE		(1 << 1)
>-#define   GEN8_CTX_FORCE_RESTORE		(1 << 2)
>-#define   GEN8_CTX_L3LLC_COHERENT		(1 << 5)
>-#define   GEN8_CTX_PRIVILEGE			(1 << 8)
>-#define   GEN8_CTX_ADDRESSING_MODE_SHIFT	3
>-#define   GEN8_CTX_ID_SHIFT			32
>-#define   GEN8_CTX_ID_WIDTH			21
>-#define   GEN11_SW_CTX_ID_SHIFT			37
>-#define   GEN11_SW_CTX_ID_WIDTH			11
>-#define   GEN11_ENGINE_CLASS_SHIFT		61
>-#define   GEN11_ENGINE_CLASS_WIDTH		3
>-#define   GEN11_ENGINE_INSTANCE_SHIFT		48
>-#define   GEN11_ENGINE_INSTANCE_WIDTH		6
>-#define   XEHP_SW_CTX_ID_SHIFT			39
>-#define   XEHP_SW_CTX_ID_WIDTH			16
>-#define   XEHP_SW_COUNTER_SHIFT			58
>-#define   XEHP_SW_COUNTER_WIDTH			6
>-
> #endif /* __INTEL_GT_REGS__ */
>diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
>index 0b76f096b559..820f8f41fc1f 100644
>--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
>+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
>@@ -69,4 +69,38 @@ void lrc_check_regs(const struct intel_context *ce,
>
> void lrc_update_runtime(struct intel_context *ce);
>
>+enum {
>+	INTEL_ADVANCED_CONTEXT = 0,
>+	INTEL_LEGACY_32B_CONTEXT,
>+	INTEL_ADVANCED_AD_CONTEXT,
>+	INTEL_LEGACY_64B_CONTEXT
>+};
>+
>+enum {
>+	FAULT_AND_HANG = 0,
>+	FAULT_AND_HALT, /* Debug only */
>+	FAULT_AND_STREAM,
>+	FAULT_AND_CONTINUE /* Unsupported */
>+};
>+
>+#define   CTX_GTT_ADDRESS_MASK			GENMASK(31, 12)

I don't like changing code while moving, but I'd open an exception here
just to fix these 2 spaces in this block. Anyway, up to you:


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>


Lucas De Marchi

>+#define   GEN8_CTX_VALID			(1 << 0)
>+#define   GEN8_CTX_FORCE_PD_RESTORE		(1 << 1)
>+#define   GEN8_CTX_FORCE_RESTORE		(1 << 2)
>+#define   GEN8_CTX_L3LLC_COHERENT		(1 << 5)
>+#define   GEN8_CTX_PRIVILEGE			(1 << 8)
>+#define   GEN8_CTX_ADDRESSING_MODE_SHIFT	3
>+#define   GEN8_CTX_ID_SHIFT			32
>+#define   GEN8_CTX_ID_WIDTH			21
>+#define   GEN11_SW_CTX_ID_SHIFT			37
>+#define   GEN11_SW_CTX_ID_WIDTH			11
>+#define   GEN11_ENGINE_CLASS_SHIFT		61
>+#define   GEN11_ENGINE_CLASS_WIDTH		3
>+#define   GEN11_ENGINE_INSTANCE_SHIFT		48
>+#define   GEN11_ENGINE_INSTANCE_WIDTH		6
>+#define   XEHP_SW_CTX_ID_SHIFT			39
>+#define   XEHP_SW_CTX_ID_WIDTH			16
>+#define   XEHP_SW_COUNTER_SHIFT			58
>+#define   XEHP_SW_COUNTER_WIDTH			6
>+
> #endif /* __INTEL_LRC_H__ */
>-- 
>2.34.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index edba18c942cf..b0982a9e4476 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -21,6 +21,7 @@ 
 #include "intel_gt.h"
 #include "intel_gt_requests.h"
 #include "intel_gt_pm.h"
+#include "intel_lrc.h"
 #include "intel_lrc_reg.h"
 #include "intel_reset.h"
 #include "intel_ring.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 69b826a3c381..84f189738a68 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1499,38 +1499,4 @@ 
 
 #define GEN12_SFC_DONE(n)			_MMIO(0x1cc000 + (n) * 0x1000)
 
-enum {
-	INTEL_ADVANCED_CONTEXT = 0,
-	INTEL_LEGACY_32B_CONTEXT,
-	INTEL_ADVANCED_AD_CONTEXT,
-	INTEL_LEGACY_64B_CONTEXT
-};
-
-enum {
-	FAULT_AND_HANG = 0,
-	FAULT_AND_HALT, /* Debug only */
-	FAULT_AND_STREAM,
-	FAULT_AND_CONTINUE /* Unsupported */
-};
-
-#define   CTX_GTT_ADDRESS_MASK			GENMASK(31, 12)
-#define   GEN8_CTX_VALID			(1 << 0)
-#define   GEN8_CTX_FORCE_PD_RESTORE		(1 << 1)
-#define   GEN8_CTX_FORCE_RESTORE		(1 << 2)
-#define   GEN8_CTX_L3LLC_COHERENT		(1 << 5)
-#define   GEN8_CTX_PRIVILEGE			(1 << 8)
-#define   GEN8_CTX_ADDRESSING_MODE_SHIFT	3
-#define   GEN8_CTX_ID_SHIFT			32
-#define   GEN8_CTX_ID_WIDTH			21
-#define   GEN11_SW_CTX_ID_SHIFT			37
-#define   GEN11_SW_CTX_ID_WIDTH			11
-#define   GEN11_ENGINE_CLASS_SHIFT		61
-#define   GEN11_ENGINE_CLASS_WIDTH		3
-#define   GEN11_ENGINE_INSTANCE_SHIFT		48
-#define   GEN11_ENGINE_INSTANCE_WIDTH		6
-#define   XEHP_SW_CTX_ID_SHIFT			39
-#define   XEHP_SW_CTX_ID_WIDTH			16
-#define   XEHP_SW_COUNTER_SHIFT			58
-#define   XEHP_SW_COUNTER_WIDTH			6
-
 #endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 0b76f096b559..820f8f41fc1f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -69,4 +69,38 @@  void lrc_check_regs(const struct intel_context *ce,
 
 void lrc_update_runtime(struct intel_context *ce);
 
+enum {
+	INTEL_ADVANCED_CONTEXT = 0,
+	INTEL_LEGACY_32B_CONTEXT,
+	INTEL_ADVANCED_AD_CONTEXT,
+	INTEL_LEGACY_64B_CONTEXT
+};
+
+enum {
+	FAULT_AND_HANG = 0,
+	FAULT_AND_HALT, /* Debug only */
+	FAULT_AND_STREAM,
+	FAULT_AND_CONTINUE /* Unsupported */
+};
+
+#define   CTX_GTT_ADDRESS_MASK			GENMASK(31, 12)
+#define   GEN8_CTX_VALID			(1 << 0)
+#define   GEN8_CTX_FORCE_PD_RESTORE		(1 << 1)
+#define   GEN8_CTX_FORCE_RESTORE		(1 << 2)
+#define   GEN8_CTX_L3LLC_COHERENT		(1 << 5)
+#define   GEN8_CTX_PRIVILEGE			(1 << 8)
+#define   GEN8_CTX_ADDRESSING_MODE_SHIFT	3
+#define   GEN8_CTX_ID_SHIFT			32
+#define   GEN8_CTX_ID_WIDTH			21
+#define   GEN11_SW_CTX_ID_SHIFT			37
+#define   GEN11_SW_CTX_ID_WIDTH			11
+#define   GEN11_ENGINE_CLASS_SHIFT		61
+#define   GEN11_ENGINE_CLASS_WIDTH		3
+#define   GEN11_ENGINE_INSTANCE_SHIFT		48
+#define   GEN11_ENGINE_INSTANCE_WIDTH		6
+#define   XEHP_SW_CTX_ID_SHIFT			39
+#define   XEHP_SW_CTX_ID_WIDTH			16
+#define   XEHP_SW_COUNTER_SHIFT			58
+#define   XEHP_SW_COUNTER_WIDTH			6
+
 #endif /* __INTEL_LRC_H__ */