Message ID | 20220503182242.18797-26-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/i915: Make fastset not suck and allow seamless M/N changes | expand |
On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Rounding to nearest is what we do for most other clock calculations > so should probably do that for M/N too. > > TODO: GOP seems to truncate instead so fastboot is going to be > a PITA to get right. Not sure what to do about it yet. Meh. Damned if you do, damned if you don't. Acked-by: Jani Nikula <jani.nikula@intel.com> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 89a7c8c1be28..c4257630a3fe 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2856,7 +2856,7 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n, > else > *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); > > - *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); > + *ret_m = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(m, *ret_n), n); > intel_reduce_m_n_ratio(ret_m, ret_n); > } > > @@ -4602,7 +4602,8 @@ int intel_dotclock_calculate(int link_freq, > if (!m_n->link_n) > return 0; > > - return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); > + return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(m_n->link_m, link_freq), > + m_n->link_n); > } > > /* Returns the currently programmed mode of the given encoder. */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 89a7c8c1be28..c4257630a3fe 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2856,7 +2856,7 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n, else *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); - *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); + *ret_m = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(m, *ret_n), n); intel_reduce_m_n_ratio(ret_m, ret_n); } @@ -4602,7 +4602,8 @@ int intel_dotclock_calculate(int link_freq, if (!m_n->link_n) return 0; - return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); + return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(m_n->link_m, link_freq), + m_n->link_n); } /* Returns the currently programmed mode of the given encoder. */