diff mbox series

[3/4] drm/i915: Pimp DPLL ref/unref debugs

Message ID 20220921211525.10675-4-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Fix TC port PLLs after readout | expand

Commit Message

Ville Syrjälä Sept. 21, 2022, 9:15 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We currently have a debug message in intel_reference_shared_dpll()
but no counterpart in intel_unreference_shared_dpll(). Add one.

Switch to the [CRTC:...] notation for the pipe name while at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

Comments

Jani Nikula Sept. 22, 2022, 11:57 a.m. UTC | #1 
On Thu, 22 Sep 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We currently have a debug message in intel_reference_shared_dpll()
> but no counterpart in intel_unreference_shared_dpll(). Add one.
>
> Switch to the [CRTC:...] notation for the pipe name while at it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e5fb66a5dd02..c21818cb6fe2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -384,20 +384,25 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
>  	if (shared_dpll[id].pipe_mask == 0)
>  		shared_dpll[id].hw_state = *pll_state;
>  
> -	drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,
> -		pipe_name(crtc->pipe));
> -
>  	shared_dpll[id].pipe_mask |= BIT(crtc->pipe);
> +
> +	drm_dbg(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
> +		crtc->base.base.id, crtc->base.name, pll->info->name);


drm_dbg_kms while at it?

>  }
>  
>  static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
>  					  const struct intel_crtc *crtc,
>  					  const struct intel_shared_dpll *pll)
>  {
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	struct intel_shared_dpll_state *shared_dpll;
>  
>  	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> +
>  	shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe);
> +
> +	drm_dbg(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
> +		crtc->base.base.id, crtc->base.name, pll->info->name);
>  }
>  
>  static void intel_put_dpll(struct intel_atomic_state *state,
Ville Syrjälä Sept. 22, 2022, 3:42 p.m. UTC | #2 
On Thu, Sep 22, 2022 at 02:57:45PM +0300, Jani Nikula wrote:
> On Thu, 22 Sep 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We currently have a debug message in intel_reference_shared_dpll()
> > but no counterpart in intel_unreference_shared_dpll(). Add one.
> >
> > Switch to the [CRTC:...] notation for the pipe name while at it.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 ++++++++---
> >  1 file changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index e5fb66a5dd02..c21818cb6fe2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -384,20 +384,25 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
> >  	if (shared_dpll[id].pipe_mask == 0)
> >  		shared_dpll[id].hw_state = *pll_state;
> >  
> > -	drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,
> > -		pipe_name(crtc->pipe));
> > -
> >  	shared_dpll[id].pipe_mask |= BIT(crtc->pipe);
> > +
> > +	drm_dbg(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
> > +		crtc->base.base.id, crtc->base.name, pll->info->name);
> 
> 
> drm_dbg_kms while at it?

I shall blame this on tab completion stopping mid-sentence.

> 
> >  }
> >  
> >  static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> >  					  const struct intel_crtc *crtc,
> >  					  const struct intel_shared_dpll *pll)
> >  {
> > +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> >  	struct intel_shared_dpll_state *shared_dpll;
> >  
> >  	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> > +
> >  	shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe);
> > +
> > +	drm_dbg(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
> > +		crtc->base.base.id, crtc->base.name, pll->info->name);
> >  }
> >  
> >  static void intel_put_dpll(struct intel_atomic_state *state,
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e5fb66a5dd02..c21818cb6fe2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -384,20 +384,25 @@  intel_reference_shared_dpll(struct intel_atomic_state *state,
 	if (shared_dpll[id].pipe_mask == 0)
 		shared_dpll[id].hw_state = *pll_state;
 
-	drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,
-		pipe_name(crtc->pipe));
-
 	shared_dpll[id].pipe_mask |= BIT(crtc->pipe);
+
+	drm_dbg(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
+		crtc->base.base.id, crtc->base.name, pll->info->name);
 }
 
 static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
 					  const struct intel_crtc *crtc,
 					  const struct intel_shared_dpll *pll)
 {
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_shared_dpll_state *shared_dpll;
 
 	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
+
 	shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe);
+
+	drm_dbg(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
+		crtc->base.base.id, crtc->base.name, pll->info->name);
 }
 
 static void intel_put_dpll(struct intel_atomic_state *state,