diff mbox series

[3/3] drm/i915/gt: Fix platform prefix

Message ID 20220930050903.3479619-4-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Improve register state context init | expand

Commit Message

Lucas De Marchi Sept. 30, 2022, 5:09 a.m. UTC 
Different handling for XeHP and later platforms should be using the
xehp prefix, not gen125. Rename them.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      | 24 +++++++++----------
 drivers/gpu/drm/i915/gt/gen8_engine_cs.h      | 12 +++++-----
 .../drm/i915/gt/intel_execlists_submission.c  |  4 ++--
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
 4 files changed, 21 insertions(+), 21 deletions(-)

Comments

Matt Roper Sept. 30, 2022, 5:56 p.m. UTC | #1 
On Thu, Sep 29, 2022 at 10:09:03PM -0700, Lucas De Marchi wrote:
> Different handling for XeHP and later platforms should be using the
> xehp prefix, not gen125. Rename them.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      | 24 +++++++++----------
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.h      | 12 +++++-----
>  .../drm/i915/gt/intel_execlists_submission.c  |  4 ++--
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
>  4 files changed, 21 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index e000eaf8abed..e1c76e5bfa82 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -396,10 +396,10 @@ int gen8_emit_init_breadcrumb(struct i915_request *rq)
>  	return 0;
>  }
>  
> -static int __gen125_emit_bb_start(struct i915_request *rq,
> -				  u64 offset, u32 len,
> -				  const unsigned int flags,
> -				  u32 arb)
> +static int __xehp_emit_bb_start(struct i915_request *rq,
> +				u64 offset, u32 len,
> +				const unsigned int flags,
> +				u32 arb)
>  {
>  	struct intel_context *ce = rq->context;
>  	u32 wa_offset = lrc_indirect_bb(ce);
> @@ -437,18 +437,18 @@ static int __gen125_emit_bb_start(struct i915_request *rq,
>  	return 0;
>  }
>  
> -int gen125_emit_bb_start_noarb(struct i915_request *rq,
> -			       u64 offset, u32 len,
> -			       const unsigned int flags)
> +int xehp_emit_bb_start_noarb(struct i915_request *rq,
> +			     u64 offset, u32 len,
> +			     const unsigned int flags)
>  {
> -	return __gen125_emit_bb_start(rq, offset, len, flags, MI_ARB_DISABLE);
> +	return __xehp_emit_bb_start(rq, offset, len, flags, MI_ARB_DISABLE);
>  }
>  
> -int gen125_emit_bb_start(struct i915_request *rq,
> -			 u64 offset, u32 len,
> -			 const unsigned int flags)
> +int xehp_emit_bb_start(struct i915_request *rq,
> +		       u64 offset, u32 len,
> +		       const unsigned int flags)
>  {
> -	return __gen125_emit_bb_start(rq, offset, len, flags, MI_ARB_ENABLE);
> +	return __xehp_emit_bb_start(rq, offset, len, flags, MI_ARB_ENABLE);
>  }
>  
>  int gen8_emit_bb_start_noarb(struct i915_request *rq,
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
> index e4d24c811dd6..655e5c00ddc2 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
> @@ -32,12 +32,12 @@ int gen8_emit_bb_start(struct i915_request *rq,
>  		       u64 offset, u32 len,
>  		       const unsigned int flags);
>  
> -int gen125_emit_bb_start_noarb(struct i915_request *rq,
> -			       u64 offset, u32 len,
> -			       const unsigned int flags);
> -int gen125_emit_bb_start(struct i915_request *rq,
> -			 u64 offset, u32 len,
> -			 const unsigned int flags);
> +int xehp_emit_bb_start_noarb(struct i915_request *rq,
> +			     u64 offset, u32 len,
> +			     const unsigned int flags);
> +int xehp_emit_bb_start(struct i915_request *rq,
> +		       u64 offset, u32 len,
> +		       const unsigned int flags);
>  
>  u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
>  u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index c718e6dc40b5..0187bc72310d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3471,9 +3471,9 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>  
>  	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
>  		if (intel_engine_has_preemption(engine))
> -			engine->emit_bb_start = gen125_emit_bb_start;
> +			engine->emit_bb_start = xehp_emit_bb_start;
>  		else
> -			engine->emit_bb_start = gen125_emit_bb_start_noarb;
> +			engine->emit_bb_start = xehp_emit_bb_start_noarb;
>  	} else {
>  		if (intel_engine_has_preemption(engine))
>  			engine->emit_bb_start = gen8_emit_bb_start;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 0ef295a94060..d81f68fef9a8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -4094,7 +4094,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>  
>  	engine->emit_bb_start = gen8_emit_bb_start;
>  	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> -		engine->emit_bb_start = gen125_emit_bb_start;
> +		engine->emit_bb_start = xehp_emit_bb_start;
>  }
>  
>  static void rcs_submission_override(struct intel_engine_cs *engine)
> -- 
> 2.37.3
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e000eaf8abed..e1c76e5bfa82 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -396,10 +396,10 @@  int gen8_emit_init_breadcrumb(struct i915_request *rq)
 	return 0;
 }
 
-static int __gen125_emit_bb_start(struct i915_request *rq,
-				  u64 offset, u32 len,
-				  const unsigned int flags,
-				  u32 arb)
+static int __xehp_emit_bb_start(struct i915_request *rq,
+				u64 offset, u32 len,
+				const unsigned int flags,
+				u32 arb)
 {
 	struct intel_context *ce = rq->context;
 	u32 wa_offset = lrc_indirect_bb(ce);
@@ -437,18 +437,18 @@  static int __gen125_emit_bb_start(struct i915_request *rq,
 	return 0;
 }
 
-int gen125_emit_bb_start_noarb(struct i915_request *rq,
-			       u64 offset, u32 len,
-			       const unsigned int flags)
+int xehp_emit_bb_start_noarb(struct i915_request *rq,
+			     u64 offset, u32 len,
+			     const unsigned int flags)
 {
-	return __gen125_emit_bb_start(rq, offset, len, flags, MI_ARB_DISABLE);
+	return __xehp_emit_bb_start(rq, offset, len, flags, MI_ARB_DISABLE);
 }
 
-int gen125_emit_bb_start(struct i915_request *rq,
-			 u64 offset, u32 len,
-			 const unsigned int flags)
+int xehp_emit_bb_start(struct i915_request *rq,
+		       u64 offset, u32 len,
+		       const unsigned int flags)
 {
-	return __gen125_emit_bb_start(rq, offset, len, flags, MI_ARB_ENABLE);
+	return __xehp_emit_bb_start(rq, offset, len, flags, MI_ARB_ENABLE);
 }
 
 int gen8_emit_bb_start_noarb(struct i915_request *rq,
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
index e4d24c811dd6..655e5c00ddc2 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
@@ -32,12 +32,12 @@  int gen8_emit_bb_start(struct i915_request *rq,
 		       u64 offset, u32 len,
 		       const unsigned int flags);
 
-int gen125_emit_bb_start_noarb(struct i915_request *rq,
-			       u64 offset, u32 len,
-			       const unsigned int flags);
-int gen125_emit_bb_start(struct i915_request *rq,
-			 u64 offset, u32 len,
-			 const unsigned int flags);
+int xehp_emit_bb_start_noarb(struct i915_request *rq,
+			     u64 offset, u32 len,
+			     const unsigned int flags);
+int xehp_emit_bb_start(struct i915_request *rq,
+		       u64 offset, u32 len,
+		       const unsigned int flags);
 
 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index c718e6dc40b5..0187bc72310d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3471,9 +3471,9 @@  logical_ring_default_vfuncs(struct intel_engine_cs *engine)
 
 	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
 		if (intel_engine_has_preemption(engine))
-			engine->emit_bb_start = gen125_emit_bb_start;
+			engine->emit_bb_start = xehp_emit_bb_start;
 		else
-			engine->emit_bb_start = gen125_emit_bb_start_noarb;
+			engine->emit_bb_start = xehp_emit_bb_start_noarb;
 	} else {
 		if (intel_engine_has_preemption(engine))
 			engine->emit_bb_start = gen8_emit_bb_start;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0ef295a94060..d81f68fef9a8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4094,7 +4094,7 @@  static void guc_default_vfuncs(struct intel_engine_cs *engine)
 
 	engine->emit_bb_start = gen8_emit_bb_start;
 	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
-		engine->emit_bb_start = gen125_emit_bb_start;
+		engine->emit_bb_start = xehp_emit_bb_start;
 }
 
 static void rcs_submission_override(struct intel_engine_cs *engine)