| Message ID | 20221207145436.1510625-1-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3,1/2] drm/i915/ddi: Align timeout for DDI_BUF_CTL active with Bspec | expand |
On Wed, Dec 07, 2022 at 08:24:36PM +0530, Ankit Nautiyal wrote: >For Gen12+ wait for 1ms for Combo Phy and 3ms for TC Phy for description here doesn't match the code as DG2 is also >= 12. Maybe just mention that the values are following the updated ones in bspec? >DDI_BUF_CTL to be active for TC phy. (Bspec:49190) > >v2: Minor refactoring for better readability. > >v3: Rebased and retained the order of checking platforms. (Imre) > >Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >--- > drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c >index 5f9a2410fc4c..c40302486b0d 100644 >--- a/drivers/gpu/drm/i915/display/intel_ddi.c >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c >@@ -185,6 +185,8 @@ void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, > enum port port) > { >+ enum phy phy = intel_port_to_phy(dev_priv, port); >+ int timeout_us; > int ret; > > /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ >@@ -193,8 +195,19 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, > return; > } > >+ if (IS_DG2(dev_priv)) { >+ timeout_us = 1200; >+ } else if (DISPLAY_VER(dev_priv) >= 12) { >+ if (intel_phy_is_tc(dev_priv, phy)) >+ timeout_us = 3000; >+ else >+ timeout_us = 1000; ADL-P should be 500 usec Lucas De Marchi >+ } else { >+ timeout_us = 500; >+ } >+ > ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & >- DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); >+ DDI_BUF_IS_IDLE), timeout_us, 10, 10); > > if (ret) > drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", >-- >2.25.1 >
Hi Lucas, Thanks for catching the issues. For ADL-P I will send a new patch to correct the timeout to 500usec. Thanks & Regards, Ankit On 12/22/2022 5:31 AM, Lucas De Marchi wrote: > On Wed, Dec 07, 2022 at 08:24:36PM +0530, Ankit Nautiyal wrote: >> For Gen12+ wait for 1ms for Combo Phy and 3ms for TC Phy for > > description here doesn't match the code as DG2 is also >= 12. > Maybe just mention that the values are following the updated ones in > bspec? > > >> DDI_BUF_CTL to be active for TC phy. (Bspec:49190) >> >> v2: Minor refactoring for better readability. >> >> v3: Rebased and retained the order of checking platforms. (Imre) >> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > > > >> --- >> drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++++++- >> 1 file changed, 14 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c >> b/drivers/gpu/drm/i915/display/intel_ddi.c >> index 5f9a2410fc4c..c40302486b0d 100644 >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c >> @@ -185,6 +185,8 @@ void intel_wait_ddi_buf_idle(struct >> drm_i915_private *dev_priv, >> static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, >> enum port port) >> { >> + enum phy phy = intel_port_to_phy(dev_priv, port); >> + int timeout_us; >> int ret; >> >> /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ >> @@ -193,8 +195,19 @@ static void intel_wait_ddi_buf_active(struct >> drm_i915_private *dev_priv, >> return; >> } >> >> + if (IS_DG2(dev_priv)) { >> + timeout_us = 1200; >> + } else if (DISPLAY_VER(dev_priv) >= 12) { >> + if (intel_phy_is_tc(dev_priv, phy)) >> + timeout_us = 3000; >> + else >> + timeout_us = 1000; > > ADL-P should be 500 usec > > Lucas De Marchi > >> + } else { >> + timeout_us = 500; >> + } >> + >> ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & >> - DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); >> + DDI_BUF_IS_IDLE), timeout_us, 10, 10); >> >> if (ret) >> drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to >> get active\n", >> -- >> 2.25.1 >>
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5f9a2410fc4c..c40302486b0d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -185,6 +185,8 @@ void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, enum port port) { + enum phy phy = intel_port_to_phy(dev_priv, port); + int timeout_us; int ret; /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ @@ -193,8 +195,19 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, return; } + if (IS_DG2(dev_priv)) { + timeout_us = 1200; + } else if (DISPLAY_VER(dev_priv) >= 12) { + if (intel_phy_is_tc(dev_priv, phy)) + timeout_us = 3000; + else + timeout_us = 1000; + } else { + timeout_us = 500; + } + ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & - DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); + DDI_BUF_IS_IDLE), timeout_us, 10, 10); if (ret) drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
For Gen12+ wait for 1ms for Combo Phy and 3ms for TC Phy for DDI_BUF_CTL to be active for TC phy. (Bspec:49190) v2: Minor refactoring for better readability. v3: Rebased and retained the order of checking platforms. (Imre) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)