diff mbox series

[v3,7/7] drm/i915/gt: Also check set bits in clr_set()

Message ID 20230630203509.1635216-8-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Fix ctx workarounds for non-masked regs | expand

Commit Message

Lucas De Marchi June 30, 2023, 8:35 p.m. UTC 
When checking if the workarounds were applied succesfully, the read-back
mask should also contain the bits being set: it's possible that in a
call to wa_write_clr_set(), the cleared bits are not a superset of the
set bits.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a6f3f160ebe2..b177c588698b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -241,13 +241,13 @@  static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg,
 static void
 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
 {
-	wa_add(wal, reg, clear, set, clear, false);
+	wa_add(wal, reg, clear, set, clear | set, false);
 }
 
 static void
 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set)
 {
-	wa_mcr_add(wal, reg, clear, set, clear, false);
+	wa_mcr_add(wal, reg, clear, set, clear | set, false);
 }
 
 static void