| Message ID | 20230907153757.2249452-21-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable Lunar Lake display | expand |
On Thu, Sep 07, 2023 at 08:37:50AM -0700, Lucas De Marchi wrote: > Xe2_LPD also needs workaround 15010685871. While adding the new display > version, also re-order the condition to follow the convention of new > version first. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index ad5251ba6fe1..cfd01050f7f1 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1841,9 +1841,10 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 > > static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) > { > - return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0)) && > - dev_priv->display.cdclk.hw.vco > 0 && > - HAS_CDCLK_SQUASH(dev_priv)); > + return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) || > + DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) || > + IS_DG2(dev_priv)) && dev_priv->display.cdclk.hw.vco > 0 && > + HAS_CDCLK_SQUASH(dev_priv); Since this workaround seems to be needed on every squashing platform from version 13 to version 20, we could probably even simplify down to IS_DISPLAY_IP_RANGE(dev_priv, IP_VER(13, 0), IP_VER(20, 0)) && ... The only risk would be if some refresh platform shows up in the future in the middle of that range in the future and doesn't need the workaround, but I'm not sure how likely that is at this point. That IP range would also technically capture ADL-P (version 13.0), but since the workaround is also conditional on HAS_CDCLK_SQUASH, it will be filtered out by that check. If you decide to keep the three platform/IP checks separate, then you can instead drop the HAS_CDCLK_SQUASH part of the condition since all affected platforms have squashing support (which is what the workaround is reprogramming). Up to you as to whether you'd rather consolidate the range or drop the redundant HAS_CDCLK_SQUASH condition, but either way, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > } > > static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > -- > 2.40.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index ad5251ba6fe1..cfd01050f7f1 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1841,9 +1841,10 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) { - return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0)) && - dev_priv->display.cdclk.hw.vco > 0 && - HAS_CDCLK_SQUASH(dev_priv)); + return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) || + DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) || + IS_DG2(dev_priv)) && dev_priv->display.cdclk.hw.vco > 0 && + HAS_CDCLK_SQUASH(dev_priv); } static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
Xe2_LPD also needs workaround 15010685871. While adding the new display version, also re-order the condition to follow the convention of new version first. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)