diff mbox series

[v3,07/25] drm/i915: During modeset forcing handle inactive but enabled pipes

Message ID 20230914192659.757475-8-imre.deak@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Improve BW management on shared display links | expand

Commit Message

Imre Deak Sept. 14, 2023, 7:26 p.m. UTC 
When forcing a modeset after a BW limit check to recompute the state of
all CRTCs on a link shared by the CRTCs, inactive but otherwise enabled
(aka DPMS off) CRTCs must be also modeset as their BW requirement may
need to be decreased.

Based on the above force-modeset inactive but enabled CRTCs as well as
required. For the current force modeset scenarios (for instance CDCLK
change) this won't make a difference, as during HW programming the
inactive CRTCs are skipped even though they are marked for a modeset.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 27e6ea21e0a91..44abe583a672d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5426,7 +5426,7 @@  static int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
 		if (IS_ERR(crtc_state))
 			return PTR_ERR(crtc_state);
 
-		if (!crtc_state->hw.active ||
+		if (!crtc_state->hw.enable ||
 		    intel_crtc_needs_modeset(crtc_state))
 			continue;