@@ -19,18 +19,13 @@
#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
#define _XELPDP_USBC1_AUX_CH_CTL 0x16f210
#define _XELPDP_USBC2_AUX_CH_CTL 0x16f410
-#define _XELPDP_USBC3_AUX_CH_CTL 0x16f610
-#define _XELPDP_USBC4_AUX_CH_CTL 0x16f810
#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, \
_DPB_AUX_CH_CTL)
-#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
- _DPA_AUX_CH_CTL, \
- _DPB_AUX_CH_CTL, \
- 0, /* port/aux_ch C is non-existent */ \
- _XELPDP_USBC1_AUX_CH_CTL, \
- _XELPDP_USBC2_AUX_CH_CTL, \
- _XELPDP_USBC3_AUX_CH_CTL, \
- _XELPDP_USBC4_AUX_CH_CTL))
+#define XELPDP_DP_AUX_CH_CTL(aux_ch) \
+ _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
+ _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL, \
+ _XELPDP_USBC1_AUX_CH_CTL, \
+ _XELPDP_USBC2_AUX_CH_CTL))
#define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
#define DP_AUX_CH_CTL_DONE REG_BIT(30)
#define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
@@ -68,17 +63,12 @@
#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
#define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214
#define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414
-#define _XELPDP_USBC3_AUX_CH_DATA1 0x16f614
-#define _XELPDP_USBC4_AUX_CH_DATA1 0x16f814
#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \
_DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
-#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
- _DPA_AUX_CH_DATA1, \
- _DPB_AUX_CH_DATA1, \
- 0, /* port/aux_ch C is non-existent */ \
- _XELPDP_USBC1_AUX_CH_DATA1, \
- _XELPDP_USBC2_AUX_CH_DATA1, \
- _XELPDP_USBC3_AUX_CH_DATA1, \
- _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) \
+ _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
+ _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1, \
+ _XELPDP_USBC1_AUX_CH_DATA1, \
+ _XELPDP_USBC2_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
#endif /* __INTEL_DP_AUX_REGS_H__ */