| Message ID | 20240306104513.2129442-4-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ALPM AUX-Less | expand |
> -----Original Message----- > From: Hogander, Jouni <jouni.hogander@intel.com> > Sent: Wednesday, March 6, 2024 4:15 PM > To: intel-gfx@lists.freedesktop.org > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Manna, Animesh > <animesh.manna@intel.com>; Murthy, Arun R <arun.r.murthy@intel.com>; > Hogander, Jouni <jouni.hogander@intel.com> > Subject: [PATCH v3 3/6] drm/i915/psr: Calculate aux less wake time > > Calculate aux less wake time and store it into alpm_params struct > > Bspec: 71477 > > v3: > - use ALPM_CTL_AUX_LESS_WAKE_TIME_MASK instead of value 63 > v2: > - use variables instead of values directly > - fix max value > - move converting port clock to Mhz into > _lnl_compute_aux_less_wake_time > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > --- > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_psr.c | 60 +++++++++++++++++++ > 2 files changed, 61 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index e67cd5b02e84..928317acc1bd 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1737,6 +1737,7 @@ struct intel_psr { > > /* LNL and beyond */ > u8 check_entry_lines; > + u8 aux_less_wake_lines; As aux-wake or aux-less is mutually exclusive can we use existing wake-line variable for aux-less as well. Regards, Animesh > } alpm_parameters; > > ktime_t last_entry_attempt; > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 6927785fd6ff..c545ee229684 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1126,6 +1126,63 @@ static bool > _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d > return true; > } > > +/* > + * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+ > + * tSilence, Max+ tPHY Establishment + tCDS) / tline) > + * For the "PHY P2 to P0" latency see the PHY Power Control page > + * (PHY P2 to P0) : > +https://gfxspecs.intel.com/Predator/Home/Index/68965 > + * : 12 us > + * The tLFPS_Period, Max term is 800ns > + * The tSilence, Max term is 180ns > + * The tPHY Establishment (a.k.a. t1) term is 50us > + * The tCDS term is 1 or 2 times t2 > + * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK > + * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1) > + * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and > + * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start > + * within the CDS period complete within the CDS period regardless of > + * entry into the period > + * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) ) > + * TPS4 Length = 252 Symbols > + */ > +static int _lnl_compute_aux_less_wake_time(int port_clock) { > + int tphy2_p2_to_p0 = 12 * 1000; > + int tlfps_period_max = 800; > + int tsilence_max = 180; > + int t1 = 50 * 1000; > + int tps4 = 252; > + int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock; > + int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1; > + int t2 = num_ml_phy_lock * tml_phy_lock; > + int tcds = 1 * t2; > + > + return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max + > tsilence_max + > + t1 + tcds, 1000); > +} > + > +static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, > + struct intel_crtc_state *crtc_state) > { > + struct drm_i915_private *i915 = dp_to_i915(intel_dp); > + int aux_less_wake_time, aux_less_wake_lines; > + > + aux_less_wake_time = > + _lnl_compute_aux_less_wake_time(crtc_state->port_clock); > + aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state- > >hw.adjusted_mode, > + aux_less_wake_time); > + > + if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK) > + return false; > + > + if (i915->display.params.psr_safest_params) > + aux_less_wake_lines = 63; > + > + intel_dp->psr.alpm_parameters.aux_less_wake_lines = > +aux_less_wake_lines; > + > + return true; > +} > + > static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, > struct intel_crtc_state *crtc_state) { @@ - > 1142,6 +1199,9 @@ static bool _lnl_compute_alpm_params(struct intel_dp > *intel_dp, > if (check_entry_lines > 15) > return false; > > + if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state)) > + return false; > + > if (i915->display.params.psr_safest_params) > check_entry_lines = 15; > > -- > 2.34.1
On Wed, 2024-03-13 at 11:14 +0000, Manna, Animesh wrote: > > > > -----Original Message----- > > From: Hogander, Jouni <jouni.hogander@intel.com> > > Sent: Wednesday, March 6, 2024 4:15 PM > > To: intel-gfx@lists.freedesktop.org > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Manna, Animesh > > <animesh.manna@intel.com>; Murthy, Arun R > > <arun.r.murthy@intel.com>; > > Hogander, Jouni <jouni.hogander@intel.com> > > Subject: [PATCH v3 3/6] drm/i915/psr: Calculate aux less wake time > > > > Calculate aux less wake time and store it into alpm_params struct > > > > Bspec: 71477 > > > > v3: > > - use ALPM_CTL_AUX_LESS_WAKE_TIME_MASK instead of value 63 > > v2: > > - use variables instead of values directly > > - fix max value > > - move converting port clock to Mhz into > > _lnl_compute_aux_less_wake_time > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > > --- > > .../drm/i915/display/intel_display_types.h | 1 + > > drivers/gpu/drm/i915/display/intel_psr.c | 60 > > +++++++++++++++++++ > > 2 files changed, 61 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index e67cd5b02e84..928317acc1bd 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -1737,6 +1737,7 @@ struct intel_psr { > > > > /* LNL and beyond */ > > u8 check_entry_lines; > > + u8 aux_less_wake_lines; > > As aux-wake or aux-less is mutually exclusive can we use existing > wake-line variable for aux-less as well. I do not have any objections here. I can do this change. BR, Jouni Högander > > Regards, > Animesh > > > } alpm_parameters; > > > > ktime_t last_entry_attempt; > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 6927785fd6ff..c545ee229684 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -1126,6 +1126,63 @@ static bool > > _compute_psr2_sdp_prior_scanline_indication(struct intel_dp > > *intel_d > > return true; > > } > > > > +/* > > + * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, > > Max+ > > + * tSilence, Max+ tPHY Establishment + tCDS) / tline) > > + * For the "PHY P2 to P0" latency see the PHY Power Control page > > + * (PHY P2 to P0) : > > +https://gfxspecs.intel.com/Predator/Home/Index/68965 > > + * : 12 us > > + * The tLFPS_Period, Max term is 800ns > > + * The tSilence, Max term is 180ns > > + * The tPHY Establishment (a.k.a. t1) term is 50us > > + * The tCDS term is 1 or 2 times t2 > > + * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK > > + * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1) > > + * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary > > and > > + * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that > > start > > + * within the CDS period complete within the CDS period regardless > > of > > + * entry into the period > > + * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) ) > > + * TPS4 Length = 252 Symbols > > + */ > > +static int _lnl_compute_aux_less_wake_time(int port_clock) { > > + int tphy2_p2_to_p0 = 12 * 1000; > > + int tlfps_period_max = 800; > > + int tsilence_max = 180; > > + int t1 = 50 * 1000; > > + int tps4 = 252; > > + int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock; > > + int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) > > + 1; > > + int t2 = num_ml_phy_lock * tml_phy_lock; > > + int tcds = 1 * t2; > > + > > + return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max + > > tsilence_max + > > + t1 + tcds, 1000); > > +} > > + > > +static int _lnl_compute_aux_less_alpm_params(struct intel_dp > > *intel_dp, > > + struct > > intel_crtc_state *crtc_state) > > { > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > + int aux_less_wake_time, aux_less_wake_lines; > > + > > + aux_less_wake_time = > > + _lnl_compute_aux_less_wake_time(crtc_state- > > >port_clock); > > + aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state- > > > hw.adjusted_mode, > > + > > aux_less_wake_time); > > + > > + if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK) > > + return false; > > + > > + if (i915->display.params.psr_safest_params) > > + aux_less_wake_lines = 63; > > + > > + intel_dp->psr.alpm_parameters.aux_less_wake_lines = > > +aux_less_wake_lines; > > + > > + return true; > > +} > > + > > static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, > > struct intel_crtc_state > > *crtc_state) { @@ - > > 1142,6 +1199,9 @@ static bool _lnl_compute_alpm_params(struct > > intel_dp > > *intel_dp, > > if (check_entry_lines > 15) > > return false; > > > > + if (!_lnl_compute_aux_less_alpm_params(intel_dp, > > crtc_state)) > > + return false; > > + > > if (i915->display.params.psr_safest_params) > > check_entry_lines = 15; > > > > -- > > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e67cd5b02e84..928317acc1bd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1737,6 +1737,7 @@ struct intel_psr { /* LNL and beyond */ u8 check_entry_lines; + u8 aux_less_wake_lines; } alpm_parameters; ktime_t last_entry_attempt; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 6927785fd6ff..c545ee229684 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1126,6 +1126,63 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d return true; } +/* + * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+ + * tSilence, Max+ tPHY Establishment + tCDS) / tline) + * For the "PHY P2 to P0" latency see the PHY Power Control page + * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965 + * : 12 us + * The tLFPS_Period, Max term is 800ns + * The tSilence, Max term is 180ns + * The tPHY Establishment (a.k.a. t1) term is 50us + * The tCDS term is 1 or 2 times t2 + * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK + * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1) + * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and + * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start + * within the CDS period complete within the CDS period regardless of + * entry into the period + * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) ) + * TPS4 Length = 252 Symbols + */ +static int _lnl_compute_aux_less_wake_time(int port_clock) +{ + int tphy2_p2_to_p0 = 12 * 1000; + int tlfps_period_max = 800; + int tsilence_max = 180; + int t1 = 50 * 1000; + int tps4 = 252; + int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock; + int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1; + int t2 = num_ml_phy_lock * tml_phy_lock; + int tcds = 1 * t2; + + return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max + tsilence_max + + t1 + tcds, 1000); +} + +static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int aux_less_wake_time, aux_less_wake_lines; + + aux_less_wake_time = + _lnl_compute_aux_less_wake_time(crtc_state->port_clock); + aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, + aux_less_wake_time); + + if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK) + return false; + + if (i915->display.params.psr_safest_params) + aux_less_wake_lines = 63; + + intel_dp->psr.alpm_parameters.aux_less_wake_lines = aux_less_wake_lines; + + return true; +} + static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -1142,6 +1199,9 @@ static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, if (check_entry_lines > 15) return false; + if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state)) + return false; + if (i915->display.params.psr_safest_params) check_entry_lines = 15;
Calculate aux less wake time and store it into alpm_params struct Bspec: 71477 v3: - use ALPM_CTL_AUX_LESS_WAKE_TIME_MASK instead of value 63 v2: - use variables instead of values directly - fix max value - move converting port clock to Mhz into _lnl_compute_aux_less_wake_time Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 60 +++++++++++++++++++ 2 files changed, 61 insertions(+)