| Message ID | 20240306144723.1826977-1-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Drop WA 16015675438 | expand |
On Wed, Mar 06, 2024 at 06:43:39AM -0800, Lucas De Marchi wrote: > With dynamic load-balancing disabled on the compute side, there's no > reason left to enable WA 16015675438. Drop it from both PVC and DG2. > Note that this can be done because now the driver always set a fixed > partition of EUs during initialization via the ccs_mode configuration. > > The flag to GuC is still needed because of 18020744125, so update > the comment accordingly. > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Acked-by: Mateusz Jablonski <mateusz.jablonski@intel.com> > Acked-by: Michal Mrozek <michal.mrozek@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > > This is the i915 counter part. The xe version of this patch > (https://lore.kernel.org/intel-xe/20240304233103.1687412-1-lucas.demarchi@intel.com/) > was already merged in drm-xe-next. I'm keeping the acked-by as it also > applies the same logic in i915. > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +----- > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +- > 2 files changed, 2 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index d67d44611c28..7f812409c30a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2928,14 +2928,10 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); > } > > - if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) { > + if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) > /* Wa_14015227452:dg2,pvc */ > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); > > - /* Wa_16015675438:dg2,pvc */ > - wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); > - } > - > if (IS_DG2(i915)) { > /* > * Wa_16011620976:dg2_g11 > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index d2b7425bbdcc..c6603793af89 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -315,7 +315,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) > if (IS_DG2_G11(gt->i915)) > flags |= GUC_WA_CONTEXT_ISOLATION; > > - /* Wa_16015675438 */ > + /* Wa_18020744125 */ > if (!RCS_MASK(gt)) > flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; > > -- > 2.43.0 >
On Mon, Mar 11, 2024 at 10:54:57AM -0400, Rodrigo Vivi wrote: >On Wed, Mar 06, 2024 at 06:43:39AM -0800, Lucas De Marchi wrote: >> With dynamic load-balancing disabled on the compute side, there's no >> reason left to enable WA 16015675438. Drop it from both PVC and DG2. >> Note that this can be done because now the driver always set a fixed >> partition of EUs during initialization via the ccs_mode configuration. >> >> The flag to GuC is still needed because of 18020744125, so update >> the comment accordingly. >> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> >> Acked-by: Mateusz Jablonski <mateusz.jablonski@intel.com> >> Acked-by: Michal Mrozek <michal.mrozek@intel.com> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > >Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> applied to drm-intel-gt-next, thanks. Lucas De Marchi
On Thu, Mar 07, 2024 at 05:24:38PM -0000, Patchwork wrote: >== Series Details == > >Series: drm/i915: Drop WA 16015675438 (rev2) >URL : https://patchwork.freedesktop.org/series/130815/ >State : failure > >== Summary == > >CI Bug Log - changes from CI_DRM_14400_full -> Patchwork_130815v2_full >==================================================== > >Summary >------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_130815v2_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_130815v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives in CI. > > > >Participating hosts (8 -> 8) >------------------------------ > > No changes in participating hosts > >Possible new issues >------------------- > > Here are the unknown changes that may have been introduced in Patchwork_130815v2_full: > >### IGT changes ### > >#### Possible regressions #### > > * igt@i915_module_load@reload-with-fault-injection: > - shard-tglu: [PASS][1] -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14400/shard-tglu-2/igt@i915_module_load@reload-with-fault-injection.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130815v2/shard-tglu-6/igt@i915_module_load@reload-with-fault-injection.html > > * igt@i915_selftest@live@requests: > - shard-mtlp: [PASS][3] -> [ABORT][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14400/shard-mtlp-3/igt@i915_selftest@live@requests.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130815v2/shard-mtlp-5/igt@i915_selftest@live@requests.html > > * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: > - shard-glk: NOTRUN -> [INCOMPLETE][5] > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130815v2/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html > > * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode: > - shard-dg2: NOTRUN -> [DMESG-WARN][6] > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130815v2/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html this is the only one that might be related since we are removing wa from pvc/dg2. But looking further, that warning shouldn't really be caused by this patch. Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index d67d44611c28..7f812409c30a 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2928,14 +2928,10 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); } - if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) { + if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) /* Wa_14015227452:dg2,pvc */ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); - /* Wa_16015675438:dg2,pvc */ - wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); - } - if (IS_DG2(i915)) { /* * Wa_16011620976:dg2_g11 diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index d2b7425bbdcc..c6603793af89 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -315,7 +315,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) if (IS_DG2_G11(gt->i915)) flags |= GUC_WA_CONTEXT_ISOLATION; - /* Wa_16015675438 */ + /* Wa_18020744125 */ if (!RCS_MASK(gt)) flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;