| Message ID | 20240306193643.1897026-2-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: cleanup dead code | expand |
On Wed, Mar 06, 2024 at 11:36:39AM -0800, Lucas De Marchi wrote: > With dynamic load-balancing disabled on the compute side, there's no > reason left to enable WA 16015675438. Drop it from both PVC and DG2. > Note that this can be done because now the driver always set a fixed > partition of EUs during initialization via the ccs_mode configuration. > > The flag to GuC is still needed because of 18020744125, so update > the comment accordingly. > > Cc: Mateusz Jablonski <mateusz.jablonski@intel.com> > Cc: Michal Mrozek <michal.mrozek@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Dynamic load-balancing disable hasn't landed in i915 yet (although it probably will soon). Assuming we wait for that to happen first before applying this, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Matt > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +----- > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +- > 2 files changed, 2 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index d67d44611c28..7f812409c30a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2928,14 +2928,10 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); > } > > - if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) { > + if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) > /* Wa_14015227452:dg2,pvc */ > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); > > - /* Wa_16015675438:dg2,pvc */ > - wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); > - } > - > if (IS_DG2(i915)) { > /* > * Wa_16011620976:dg2_g11 > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index d2b7425bbdcc..c6603793af89 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -315,7 +315,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) > if (IS_DG2_G11(gt->i915)) > flags |= GUC_WA_CONTEXT_ISOLATION; > > - /* Wa_16015675438 */ > + /* Wa_18020744125 */ > if (!RCS_MASK(gt)) > flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; > > -- > 2.43.0 >
On Tue, Mar 12, 2024 at 03:54:09PM -0700, Matt Roper wrote: >On Wed, Mar 06, 2024 at 11:36:39AM -0800, Lucas De Marchi wrote: >> With dynamic load-balancing disabled on the compute side, there's no >> reason left to enable WA 16015675438. Drop it from both PVC and DG2. >> Note that this can be done because now the driver always set a fixed >> partition of EUs during initialization via the ccs_mode configuration. >> >> The flag to GuC is still needed because of 18020744125, so update >> the comment accordingly. >> >> Cc: Mateusz Jablonski <mateusz.jablonski@intel.com> >> Cc: Michal Mrozek <michal.mrozek@intel.com> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > >Dynamic load-balancing disable hasn't landed in i915 yet (although it >probably will soon). Assuming we wait for that to happen first before >applying this, > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Humn... I probably grepped the wrong tree for this one since I was seeing ccs_mode being set. Indeed it isn't :-/, so I will have to land a fix or revert since this patch already landed a few days ago. Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index d67d44611c28..7f812409c30a 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2928,14 +2928,10 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); } - if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) { + if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) /* Wa_14015227452:dg2,pvc */ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); - /* Wa_16015675438:dg2,pvc */ - wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); - } - if (IS_DG2(i915)) { /* * Wa_16011620976:dg2_g11 diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index d2b7425bbdcc..c6603793af89 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -315,7 +315,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) if (IS_DG2_G11(gt->i915)) flags |= GUC_WA_CONTEXT_ISOLATION; - /* Wa_16015675438 */ + /* Wa_18020744125 */ if (!RCS_MASK(gt)) flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
With dynamic load-balancing disabled on the compute side, there's no reason left to enable WA 16015675438. Drop it from both PVC and DG2. Note that this can be done because now the driver always set a fixed partition of EUs during initialization via the ccs_mode configuration. The flag to GuC is still needed because of 18020744125, so update the comment accordingly. Cc: Mateusz Jablonski <mateusz.jablonski@intel.com> Cc: Michal Mrozek <michal.mrozek@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +----- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +- 2 files changed, 2 insertions(+), 6 deletions(-)