| Message ID | 20240320201152.3487892-3-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dp: Few MTL/DSC and a UHBR monitor fix | expand |
On 3/21/2024 1:41 AM, Imre Deak wrote: > The expected link symbol clock unit when calculating the DSC DPT bpp > limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit > based on the crtc clock. As opposed to this port_clock is used - which > has a 10 kbits/sec unit - with the resulting symbol clock in 10 > kSymbols/sec units (disregarding the rounding error for the 13.5Gbps > rate). Fix the calculation using the expected 10x factor. > > Signed-off-by: Imre Deak <imre.deak@intel.com> LGTM. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 53aec023ce92f..b2bcf66071b05 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -58,8 +58,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp > { > if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { > int output_bpp = bpp; > - /* DisplayPort 2 128b/132b, bits per lane is always 32 */ > - int symbol_clock = crtc_state->port_clock / 32; > + int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); > > if (output_bpp * adjusted_mode->crtc_clock >= > symbol_clock * 72) {
On Tue, Mar 26, 2024 at 3:01 AM Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> wrote: > > > On 3/21/2024 1:41 AM, Imre Deak wrote: > > The expected link symbol clock unit when calculating the DSC DPT bpp > > limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit > > based on the crtc clock. As opposed to this port_clock is used - which > > has a 10 kbits/sec unit - with the resulting symbol clock in 10 > > kSymbols/sec units (disregarding the rounding error for the 13.5Gbps > > rate). Fix the calculation using the expected 10x factor. > > > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > LGTM. > > Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > > > --- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > index 53aec023ce92f..b2bcf66071b05 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -58,8 +58,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp > > { > > if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { > > int output_bpp = bpp; > > - /* DisplayPort 2 128b/132b, bits per lane is always 32 */ > > - int symbol_clock = crtc_state->port_clock / 32; > > + int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); Is this correct Symbol clock calculation not needed for UHBR support on platforms with DISPLAY_VER = 14 (MTL)? Manasi > > > > if (output_bpp * adjusted_mode->crtc_clock >= > > symbol_clock * 72) {
On Tue, Mar 26, 2024 at 1:04 PM Manasi Navare <navaremanasi@chromium.org> wrote: > > On Tue, Mar 26, 2024 at 3:01 AM Nautiyal, Ankit K > <ankit.k.nautiyal@intel.com> wrote: > > > > > > On 3/21/2024 1:41 AM, Imre Deak wrote: > > > The expected link symbol clock unit when calculating the DSC DPT bpp > > > limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit > > > based on the crtc clock. As opposed to this port_clock is used - which > > > has a 10 kbits/sec unit - with the resulting symbol clock in 10 > > > kSymbols/sec units (disregarding the rounding error for the 13.5Gbps > > > rate). Fix the calculation using the expected 10x factor. > > > > > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > > > LGTM. > > > > Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > > > > > --- > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +-- > > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > index 53aec023ce92f..b2bcf66071b05 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > @@ -58,8 +58,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp > > > { > > > if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { > > > int output_bpp = bpp; > > > - /* DisplayPort 2 128b/132b, bits per lane is always 32 */ > > > - int symbol_clock = crtc_state->port_clock / 32; > > > + int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); > > Is this correct Symbol clock calculation not needed for UHBR support > on platforms with DISPLAY_VER = 14 (MTL)? > > Manasi Never mind, the patch [PATCH 05/11] drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL answers my question here Manasi > > > > > > if (output_bpp * adjusted_mode->crtc_clock >= > > > symbol_clock * 72) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 53aec023ce92f..b2bcf66071b05 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -58,8 +58,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp { if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { int output_bpp = bpp; - /* DisplayPort 2 128b/132b, bits per lane is always 32 */ - int symbol_clock = crtc_state->port_clock / 32; + int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); if (output_bpp * adjusted_mode->crtc_clock >= symbol_clock * 72) {
The expected link symbol clock unit when calculating the DSC DPT bpp limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit based on the crtc clock. As opposed to this port_clock is used - which has a 10 kbits/sec unit - with the resulting symbol clock in 10 kSymbols/sec units (disregarding the rounding error for the 13.5Gbps rate). Fix the calculation using the expected 10x factor. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)