| Message ID | 20240320201152.3487892-5-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dp: Few MTL/DSC and a UHBR monitor fix | expand |
On 3/21/2024 1:41 AM, Imre Deak wrote: > The DSC DPT interface BW limit check should take into account the link > clock's (aka DDI clock in bspec) channel coding efficiency overhead. > Bspec doesn't mention this, however this matches how the link BW limit > is checked (that is the BW limit on wire as opposed to the above DPT > limit) for which Bspec doesn't mention the overhead either. > > This fixes the DPT bpp limit for at least the 5k@60Hz/DSC mode on a Dell > UHBR monitor/link I tested. > > Bspec: 49259 > > Signed-off-by: Imre Deak <imre.deak@intel.com> LGTM. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index c21fd7a2cd44f..79f34be5c89da 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -59,11 +59,14 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp > if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { > int output_bpp = bpp; > int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); > + int available_bw = mul_u32_u32(symbol_clock * 72, > + drm_dp_bw_channel_coding_efficiency(true)) / > + 1000000; > > if (output_bpp * adjusted_mode->crtc_clock > > - symbol_clock * 72) { > + available_bw) { > drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n", > - output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72); > + output_bpp * adjusted_mode->crtc_clock, available_bw); > return -EINVAL; > } > }
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c21fd7a2cd44f..79f34be5c89da 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -59,11 +59,14 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { int output_bpp = bpp; int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); + int available_bw = mul_u32_u32(symbol_clock * 72, + drm_dp_bw_channel_coding_efficiency(true)) / + 1000000; if (output_bpp * adjusted_mode->crtc_clock > - symbol_clock * 72) { + available_bw) { drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n", - output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72); + output_bpp * adjusted_mode->crtc_clock, available_bw); return -EINVAL; } }
The DSC DPT interface BW limit check should take into account the link clock's (aka DDI clock in bspec) channel coding efficiency overhead. Bspec doesn't mention this, however this matches how the link BW limit is checked (that is the BW limit on wire as opposed to the above DPT limit) for which Bspec doesn't mention the overhead either. This fixes the DPT bpp limit for at least the 5k@60Hz/DSC mode on a Dell UHBR monitor/link I tested. Bspec: 49259 Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)