| Message ID | 20240329011254.24160-21-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Bigjoiner modeset sequence redesign and MST support | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville > Syrjala > Sent: Friday, March 29, 2024 6:43 AM > To: intel-gfx@lists.freedesktop.org > Cc: Srinivas, Vidya <vidya.srinivas@intel.com> > Subject: [PATCH 20/22] drm/i915/mst: Add bigjoiner handling to MST modeset > sequence > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Loop over all joined pipes at relevant points in the MST modeset sequence. > > Carved out from Vidya's earlier big patch, with naming/etc. > changed to match the earlier hsw_crtc_enable() stuff. > > Co-developed-by: Vidya Srinivas <vidya.srinivas@intel.com> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Thanks and Regards, Arun R Murthy -------------------- > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 34 ++++++++++++++++----- > 1 file changed, 27 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index de364ed77c08..2d601d214915 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -956,6 +956,7 @@ static void intel_mst_post_disable_dp(struct > intel_atomic_state *state, > struct drm_dp_mst_atomic_payload *new_payload = > drm_atomic_get_mst_payload_state(new_mst_state, > connector->port); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > + struct intel_crtc *pipe_crtc; > bool last_mst_stream; > > intel_dp->active_mst_links--; > @@ -964,7 +965,13 @@ static void intel_mst_post_disable_dp(struct > intel_atomic_state *state, > DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && > !intel_dp_mst_is_master_trans(old_crtc_state)); > > - intel_crtc_vblank_off(old_crtc_state); > + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, > + > intel_crtc_joined_pipe_mask(old_crtc_state)) { > + const struct intel_crtc_state *old_pipe_crtc_state = > + intel_atomic_get_old_crtc_state(state, pipe_crtc); > + > + intel_crtc_vblank_off(old_pipe_crtc_state); > + } > > intel_disable_transcoder(old_crtc_state); > > @@ -982,12 +989,18 @@ static void intel_mst_post_disable_dp(struct > intel_atomic_state *state, > > intel_ddi_disable_transcoder_func(old_crtc_state); > > - intel_dsc_disable(old_crtc_state); > + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, > + > intel_crtc_joined_pipe_mask(old_crtc_state)) { > + const struct intel_crtc_state *old_pipe_crtc_state = > + intel_atomic_get_old_crtc_state(state, pipe_crtc); > > - if (DISPLAY_VER(dev_priv) >= 9) > - skl_scaler_disable(old_crtc_state); > - else > - ilk_pfit_disable(old_crtc_state); > + intel_dsc_disable(old_pipe_crtc_state); > + > + if (DISPLAY_VER(dev_priv) >= 9) > + skl_scaler_disable(old_pipe_crtc_state); > + else > + ilk_pfit_disable(old_pipe_crtc_state); > + } > > /* > * Power down mst path before disabling the port, otherwise we end > @@ -1133,6 +1146,7 @@ static void intel_mst_enable_dp(struct > intel_atomic_state *state, > drm_atomic_get_new_mst_topology_state(&state->base, > &intel_dp->mst_mgr); > enum transcoder trans = pipe_config->cpu_transcoder; > bool first_mst_stream = intel_dp->active_mst_links == 1; > + struct intel_crtc *pipe_crtc; > > drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); > > @@ -1174,7 +1188,13 @@ static void intel_mst_enable_dp(struct > intel_atomic_state *state, > > intel_enable_transcoder(pipe_config); > > - intel_crtc_vblank_on(pipe_config); > + for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, > + > intel_crtc_joined_pipe_mask(pipe_config)) { > + const struct intel_crtc_state *pipe_crtc_state = > + intel_atomic_get_new_crtc_state(state, pipe_crtc); > + > + intel_crtc_vblank_on(pipe_crtc_state); > + } > > intel_hdcp_enable(state, encoder, pipe_config, conn_state); } > -- > 2.43.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index de364ed77c08..2d601d214915 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -956,6 +956,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, struct drm_dp_mst_atomic_payload *new_payload = drm_atomic_get_mst_payload_state(new_mst_state, connector->port); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_crtc *pipe_crtc; bool last_mst_stream; intel_dp->active_mst_links--; @@ -964,7 +965,13 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && !intel_dp_mst_is_master_trans(old_crtc_state)); - intel_crtc_vblank_off(old_crtc_state); + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, + intel_crtc_joined_pipe_mask(old_crtc_state)) { + const struct intel_crtc_state *old_pipe_crtc_state = + intel_atomic_get_old_crtc_state(state, pipe_crtc); + + intel_crtc_vblank_off(old_pipe_crtc_state); + } intel_disable_transcoder(old_crtc_state); @@ -982,12 +989,18 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, intel_ddi_disable_transcoder_func(old_crtc_state); - intel_dsc_disable(old_crtc_state); + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, + intel_crtc_joined_pipe_mask(old_crtc_state)) { + const struct intel_crtc_state *old_pipe_crtc_state = + intel_atomic_get_old_crtc_state(state, pipe_crtc); - if (DISPLAY_VER(dev_priv) >= 9) - skl_scaler_disable(old_crtc_state); - else - ilk_pfit_disable(old_crtc_state); + intel_dsc_disable(old_pipe_crtc_state); + + if (DISPLAY_VER(dev_priv) >= 9) + skl_scaler_disable(old_pipe_crtc_state); + else + ilk_pfit_disable(old_pipe_crtc_state); + } /* * Power down mst path before disabling the port, otherwise we end @@ -1133,6 +1146,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr); enum transcoder trans = pipe_config->cpu_transcoder; bool first_mst_stream = intel_dp->active_mst_links == 1; + struct intel_crtc *pipe_crtc; drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); @@ -1174,7 +1188,13 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, intel_enable_transcoder(pipe_config); - intel_crtc_vblank_on(pipe_config); + for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, + intel_crtc_joined_pipe_mask(pipe_config)) { + const struct intel_crtc_state *pipe_crtc_state = + intel_atomic_get_new_crtc_state(state, pipe_crtc); + + intel_crtc_vblank_on(pipe_crtc_state); + } intel_hdcp_enable(state, encoder, pipe_config, conn_state); }