diff mbox series

[v9,09/12] drm/i915/psr: Do not apply workarounds in case of panel replay

Message ID 20240503063413.1008135-10-jouni.hogander@intel.com (mailing list archive)
State New
Headers show
Series Panel replay selective update support | expand

Commit Message

Hogander, Jouni May 3, 2024, 6:34 a.m. UTC 
There are some workarounds that are not applicable for panel replay. Do not
apply these if panel replay is used.

Bspec: 66624, 50422

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c  |  5 +++--
 drivers/gpu/drm/i915/display/intel_hdmi.c |  3 ++-
 drivers/gpu/drm/i915/display/intel_psr.c  | 16 ++++++++++------
 3 files changed, 15 insertions(+), 9 deletions(-)

Comments

Animesh Manna May 9, 2024, 3:15 p.m. UTC | #1 
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: [PATCH v9 09/12] drm/i915/psr: Do not apply workarounds in case
> of panel replay
> 
> There are some workarounds that are not applicable for panel replay. Do not
> apply these if panel replay is used.
> 
> Bspec: 66624, 50422
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c  |  5 +++--
> drivers/gpu/drm/i915/display/intel_hdmi.c |  3 ++-
> drivers/gpu/drm/i915/display/intel_psr.c  | 16 ++++++++++------
>  3 files changed, 15 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 984f13d8c0c8..50dd8eb9012e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1251,7 +1251,8 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>  	 * Recommendation is to keep this combination disabled
>  	 * Bspec: 50422 HSD: 14010260002
>  	 */
> -	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
> +	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update &&
> +	    !crtc_state->has_panel_replay) {
>  		plane_state->no_fbc_reason = "PSR2 enabled";
>  		return 0;
>  	}
> @@ -1259,7 +1260,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>  	/* Wa_14016291713 */
>  	if ((IS_DISPLAY_VER(i915, 12, 13) ||
>  	     IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
> -	    crtc_state->has_psr) {
> +	    crtc_state->has_psr && !crtc_state->has_panel_replay) {
>  		plane_state->no_fbc_reason = "PSR1 enabled
> (Wa_14016291713)";
>  		return 0;
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 5f6deceaf8ba..0faf2afa1c09 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -532,7 +532,8 @@ void hsw_write_infoframe(struct intel_encoder
> *encoder,
>  			       0);
> 
>  	/* Wa_14013475917 */
> -	if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr &&
> type == DP_SDP_VSC))
> +	if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr &&
> +	      !crtc_state->has_panel_replay && type == DP_SDP_VSC))
>  		val |= hsw_infoframe_enable(type);
> 
>  	if (type == DP_SDP_VSC)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8f23df5cd5a8..f2eca0db47fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1959,13 +1959,15 @@ static void intel_psr_enable_source(struct
> intel_dp *intel_dp,
>  		 * All supported adlp panels have 1-based X granularity, this
> may
>  		 * cause issues if non-supported panels are used.
>  		 */
> -		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0) ||
> -		    IS_ALDERLAKE_P(dev_priv))
> +		if (!intel_dp->psr.panel_replay_enabled &&
> +		    (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0) ||
> +		     IS_ALDERLAKE_P(dev_priv)))
>  			intel_de_rmw(dev_priv,
> hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
>  				     0, ADLP_1_BASED_X_GRANULARITY);
> 
>  		/* Wa_16012604467:adlp,mtl[a0,b0] */
> -		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
> +		if (!intel_dp->psr.panel_replay_enabled &&
> +		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
> 
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
> 
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> @@ -2141,7 +2143,8 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
> 
>  	if (intel_dp->psr.sel_update_enabled) {
>  		/* Wa_16012604467:adlp,mtl[a0,b0] */
> -		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
> +		if (!intel_dp->psr.panel_replay_enabled &&
> +		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
>  			intel_de_rmw(dev_priv,
> 
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> 
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -2627,8 +2630,9
> @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  		goto skip_sel_fetch_set_loop;
> 
>  	/* Wa_14014971492 */
> -	if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)
> ||
> -	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> +	if (!crtc_state->has_panel_replay &&
> +	    ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)
> ||
> +	      IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) &&
>  	    crtc_state->splitter.enable)
>  		crtc_state->psr2_su_area.y1 = 0;
> 
> --
> 2.34.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 984f13d8c0c8..50dd8eb9012e 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1251,7 +1251,8 @@  static int intel_fbc_check_plane(struct intel_atomic_state *state,
 	 * Recommendation is to keep this combination disabled
 	 * Bspec: 50422 HSD: 14010260002
 	 */
-	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
+	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update &&
+	    !crtc_state->has_panel_replay) {
 		plane_state->no_fbc_reason = "PSR2 enabled";
 		return 0;
 	}
@@ -1259,7 +1260,7 @@  static int intel_fbc_check_plane(struct intel_atomic_state *state,
 	/* Wa_14016291713 */
 	if ((IS_DISPLAY_VER(i915, 12, 13) ||
 	     IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
-	    crtc_state->has_psr) {
+	    crtc_state->has_psr && !crtc_state->has_panel_replay) {
 		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
 		return 0;
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 5f6deceaf8ba..0faf2afa1c09 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -532,7 +532,8 @@  void hsw_write_infoframe(struct intel_encoder *encoder,
 			       0);
 
 	/* Wa_14013475917 */
-	if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC))
+	if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr &&
+	      !crtc_state->has_panel_replay && type == DP_SDP_VSC))
 		val |= hsw_infoframe_enable(type);
 
 	if (type == DP_SDP_VSC)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8f23df5cd5a8..f2eca0db47fd 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1959,13 +1959,15 @@  static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 * All supported adlp panels have 1-based X granularity, this may
 		 * cause issues if non-supported panels are used.
 		 */
-		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
-		    IS_ALDERLAKE_P(dev_priv))
+		if (!intel_dp->psr.panel_replay_enabled &&
+		    (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
+		     IS_ALDERLAKE_P(dev_priv)))
 			intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
 				     0, ADLP_1_BASED_X_GRANULARITY);
 
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
+		if (!intel_dp->psr.panel_replay_enabled &&
+		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -2141,7 +2143,8 @@  static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	if (intel_dp->psr.sel_update_enabled) {
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
+		if (!intel_dp->psr.panel_replay_enabled &&
+		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -2627,8 +2630,9 @@  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		goto skip_sel_fetch_set_loop;
 
 	/* Wa_14014971492 */
-	if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
-	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
+	if (!crtc_state->has_panel_replay &&
+	    ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
+	      IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) &&
 	    crtc_state->splitter.enable)
 		crtc_state->psr2_su_area.y1 = 0;