Message ID | 20240510152329.24098-9-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | drm/i915: skl+ plane register stuff | expand |
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane > and just use the real thing. > > Cc: Zhenyu Wang <zhenyuw@linux.intel.com> > CC: Zhi Wang <zhi.wang.linux@gmail.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> The original is a baffling mix. Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index b53c98cd6d7f..843bdb46d49c 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -1030,12 +1030,12 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) > MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1)); > MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2)); > MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3)); > - MMIO_D(_MMIO(_PLANE_CTL_3_A)); > - MMIO_D(_MMIO(_PLANE_CTL_3_B)); > - MMIO_D(_MMIO(0x72380)); > - MMIO_D(_MMIO(0x7239c)); > - MMIO_D(_MMIO(_PLANE_SURF_3_A)); > - MMIO_D(_MMIO(_PLANE_SURF_3_B)); > + MMIO_D(PLANE_CTL(PIPE_A, 2)); > + MMIO_D(PLANE_CTL(PIPE_B, 2)); > + MMIO_D(PLANE_CTL(PIPE_C, 2)); > + MMIO_D(PLANE_SURF(PIPE_A, 2)); > + MMIO_D(PLANE_SURF(PIPE_B, 2)); > + MMIO_D(PLANE_SURF(PIPE_C, 2)); > MMIO_D(DMC_SSP_BASE); > MMIO_D(DMC_HTP_SKL); > MMIO_D(DMC_LAST_WRITE);
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index b53c98cd6d7f..843bdb46d49c 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -1030,12 +1030,12 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1)); MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2)); MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3)); - MMIO_D(_MMIO(_PLANE_CTL_3_A)); - MMIO_D(_MMIO(_PLANE_CTL_3_B)); - MMIO_D(_MMIO(0x72380)); - MMIO_D(_MMIO(0x7239c)); - MMIO_D(_MMIO(_PLANE_SURF_3_A)); - MMIO_D(_MMIO(_PLANE_SURF_3_B)); + MMIO_D(PLANE_CTL(PIPE_A, 2)); + MMIO_D(PLANE_CTL(PIPE_B, 2)); + MMIO_D(PLANE_CTL(PIPE_C, 2)); + MMIO_D(PLANE_SURF(PIPE_A, 2)); + MMIO_D(PLANE_SURF(PIPE_B, 2)); + MMIO_D(PLANE_SURF(PIPE_C, 2)); MMIO_D(DMC_SSP_BASE); MMIO_D(DMC_HTP_SKL); MMIO_D(DMC_LAST_WRITE);