| Message ID | 60989a3cf3d5c449356f5d827caf0ab5bfe3b528.1574775655.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dsi: enable DSC | expand |
> -----Original Message----- > From: Jani Nikula <jani.nikula@intel.com> > Sent: Tuesday, November 26, 2019 7:13 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita > <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com> > Subject: [PATCH v3 12/13] drm/i915/dsi: account for DSC in horizontal > timings > > When DSC is enabled, we need to adjust the horizontal timings to account > for the compressed (and therefore reduced) link speed. > > The compressed frequency ratio simplifies down to the ratio between > compressed and non-compressed bpp. > > Bspec: 49263 > Suggested-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Can be considered out of this patch, but gen11_dsi_get_timings would need corresponding Changes to avoid state mismatch wrt horizontal timings. Other than that, this patch looks good to me. Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Thanks, Vandita > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 24 +++++++++++++++++++----- > 1 file changed, 19 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > b/drivers/gpu/drm/i915/display/icl_dsi.c > index 460759913708..caa477c4b1af 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -785,12 +785,12 @@ gen11_dsi_configure_transcoder(struct > intel_encoder *encoder, > > static void > gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, > - const struct intel_crtc_state *pipe_config) > + const struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > const struct drm_display_mode *adjusted_mode = > - &pipe_config->hw.adjusted_mode; > + &crtc_state->hw.adjusted_mode; > enum port port; > enum transcoder dsi_trans; > /* horizontal timings */ > @@ -798,11 +798,25 @@ gen11_dsi_set_transcoder_timings(struct > intel_encoder *encoder, > u16 hback_porch; > /* vertical timings */ > u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; > + int mul = 1, div = 1; > + > + /* > + * Adjust horizontal timings (htotal, hsync_start, hsync_end) to > account > + * for slower link speed if DSC is enabled. > + * > + * The compression frequency ratio is the ratio between compressed > and > + * non-compressed link speeds, and simplifies down to the ratio > between > + * compressed and non-compressed bpp. > + */ > + if (crtc_state->dsc.compression_enable) { > + mul = crtc_state->dsc.compressed_bpp; > + div = mipi_dsi_pixel_format_to_bpp(intel_dsi- > >pixel_format); > + } > > hactive = adjusted_mode->crtc_hdisplay; > - htotal = adjusted_mode->crtc_htotal; > - hsync_start = adjusted_mode->crtc_hsync_start; > - hsync_end = adjusted_mode->crtc_hsync_end; > + htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); > + hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * > mul, div); > + hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * > mul, div); > hsync_size = hsync_end - hsync_start; > hback_porch = (adjusted_mode->crtc_htotal - > adjusted_mode->crtc_hsync_end); > -- > 2.20.1
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 460759913708..caa477c4b1af 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -785,12 +785,12 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, static void gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, - const struct intel_crtc_state *pipe_config) + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); const struct drm_display_mode *adjusted_mode = - &pipe_config->hw.adjusted_mode; + &crtc_state->hw.adjusted_mode; enum port port; enum transcoder dsi_trans; /* horizontal timings */ @@ -798,11 +798,25 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, u16 hback_porch; /* vertical timings */ u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; + int mul = 1, div = 1; + + /* + * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account + * for slower link speed if DSC is enabled. + * + * The compression frequency ratio is the ratio between compressed and + * non-compressed link speeds, and simplifies down to the ratio between + * compressed and non-compressed bpp. + */ + if (crtc_state->dsc.compression_enable) { + mul = crtc_state->dsc.compressed_bpp; + div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); + } hactive = adjusted_mode->crtc_hdisplay; - htotal = adjusted_mode->crtc_htotal; - hsync_start = adjusted_mode->crtc_hsync_start; - hsync_end = adjusted_mode->crtc_hsync_end; + htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); + hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); + hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); hsync_size = hsync_end - hsync_start; hback_porch = (adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end);
When DSC is enabled, we need to adjust the horizontal timings to account for the compressed (and therefore reduced) link speed. The compressed frequency ratio simplifies down to the ratio between compressed and non-compressed bpp. Bspec: 49263 Suggested-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-)