| Message ID | 653bf9815d562f02c7247c6b66b85b243f3172e7.1655306128.git.mchehab@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix TLB invalidate issues with Broadwell | expand |
On Wed, Jun 15, 2022 at 04:27:36PM +0100, Mauro Carvalho Chehab wrote: >From: Chris Wilson <chris.p.wilson@intel.com> > >On gen12 HW, ensure that the TLB of the OA unit is also invalidated >as just invalidating the TLB of an engine is not enough. > >Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > >Signed-off-by: Chris Wilson <chris.p.wilson@intel.com> >Cc: Fei Yang <fei.yang@intel.com> >Cc: Andi Shyti <andi.shyti@linux.intel.com> >Cc: stable@vger.kernel.org >Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> >Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org> >--- > >See [PATCH 0/6] at: https://lore.kernel.org/all/cover.1655306128.git.mchehab@kernel.org/ > > drivers/gpu/drm/i915/gt/intel_gt.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > >diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c >index d5ed6a6ac67c..61b7ec5118f9 100644 >--- a/drivers/gpu/drm/i915/gt/intel_gt.c >+++ b/drivers/gpu/drm/i915/gt/intel_gt.c >@@ -10,6 +10,7 @@ > #include "pxp/intel_pxp.h" > > #include "i915_drv.h" >+#include "i915_perf_oa_regs.h" > #include "intel_context.h" > #include "intel_engine_pm.h" > #include "intel_engine_regs.h" >@@ -1259,6 +1260,15 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) > awake |= engine->mask; > } > >+ /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */ >+ if (awake && >+ (IS_TIGERLAKE(i915) || >+ IS_DG1(i915) || >+ IS_ROCKETLAKE(i915) || >+ IS_ALDERLAKE_S(i915) || >+ IS_ALDERLAKE_P(i915))) >+ intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1); >+ This patch can be dropped since this is being done in i915/i915_perf.c -> gen12_oa_disable and is synchronized with OA use cases. Regards, Umesh > for_each_engine_masked(engine, gt, awake, tmp) { > struct reg_and_bit rb; > >-- >2.36.1 >
Hi Mauro, On Wed, Jun 15, 2022 at 04:27:36PM +0100, Mauro Carvalho Chehab wrote: > From: Chris Wilson <chris.p.wilson@intel.com> > > On gen12 HW, ensure that the TLB of the OA unit is also invalidated > as just invalidating the TLB of an engine is not enough. > > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > > Signed-off-by: Chris Wilson <chris.p.wilson@intel.com> > Cc: Fei Yang <fei.yang@intel.com> > Cc: Andi Shyti <andi.shyti@linux.intel.com> > Cc: stable@vger.kernel.org > Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> > Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Thanks, Andi
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index d5ed6a6ac67c..61b7ec5118f9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -10,6 +10,7 @@ #include "pxp/intel_pxp.h" #include "i915_drv.h" +#include "i915_perf_oa_regs.h" #include "intel_context.h" #include "intel_engine_pm.h" #include "intel_engine_regs.h" @@ -1259,6 +1260,15 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) awake |= engine->mask; } + /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */ + if (awake && + (IS_TIGERLAKE(i915) || + IS_DG1(i915) || + IS_ROCKETLAKE(i915) || + IS_ALDERLAKE_S(i915) || + IS_ALDERLAKE_P(i915))) + intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1); + for_each_engine_masked(engine, gt, awake, tmp) { struct reg_and_bit rb;