@@ -1330,9 +1330,11 @@ static int gen8_update_plane_mmio_from_mi_display_flip(
if (info->plane == PLANE_PRIMARY)
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
- if (info->async_flip)
+ if (info->async_flip) {
intel_vgpu_trigger_virtual_event(vgpu, info->event);
- else
+ set_bit(info->plane,
+ vgpu->display.async_flip_event[info->pipe]);
+ } else
set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
return 0;
@@ -420,6 +420,16 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
intel_vgpu_trigger_virtual_event(vgpu, event);
}
+ for_each_set_bit(event, vgpu->display.async_flip_event[pipe],
+ I915_MAX_PLANES) {
+ clear_bit(event, vgpu->display.async_flip_event[pipe]);
+ if (!pipe_is_enabled(vgpu, pipe))
+ continue;
+
+ if (event == PLANE_PRIMARY)
+ eventfd_signal_val |= DISPLAY_PRI_REFRESH_EVENT_VAL;
+ }
+
if (eventfd_signal_val)
no_pageflip_count = 0;
else if (!eventfd_signal_val && no_pageflip_count > PAGEFLIP_DELAY_THR)
@@ -128,6 +128,8 @@ struct intel_vgpu_display {
struct intel_vgpu_i2c_edid i2c_edid;
struct intel_vgpu_port ports[I915_MAX_PORTS];
struct intel_vgpu_sbi sbi;
+ DECLARE_BITMAP(async_flip_event[I915_MAX_PIPES],
+ I915_MAX_PLANES);
};
struct vgpu_sched_ctl {
@@ -758,9 +758,10 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
- if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)
+ if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) {
intel_vgpu_trigger_virtual_event(vgpu, event);
- else
+ set_bit(PLANE_PRIMARY, vgpu->display.async_flip_event[pipe]);
+ } else
set_bit(event, vgpu->irq.flip_done_event[pipe]);
return 0;