diff mbox series

[kvm-unit-tests,4/4] nVMX: Extend EPT cap MSR test to allow 5-level EPT

Message ID 20200207174244.6590-5-sean.j.christopherson@intel.com (mailing list archive)
State New, archived
Headers show
Series nVMX: 5-level nested EPT support | expand

Commit Message

Sean Christopherson Feb. 7, 2020, 5:42 p.m. UTC 
Modify the EMSR_IA32_VMX_EPT_VPID_CAP test to mark the 5-level EPT cap
bit as allowed-1. KVM is in the process of gaining support for 5-level
nested EPT[*].

[*] https://lkml.kernel.org/r/20200206220836.22743-1-sean.j.christopherson@intel.com

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
 x86/vmx.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/x86/vmx.c b/x86/vmx.c
index ac4aa56..a15c2be 100644
--- a/x86/vmx.c
+++ b/x86/vmx.c
@@ -1540,6 +1540,7 @@  static void test_vmx_caps(void)
 	fixed0 = -1ull;
 	fixed0 &= ~(EPT_CAP_WT |
 		    EPT_CAP_PWL4 |
+		    EPT_CAP_PWL5 |
 		    EPT_CAP_UC |
 		    EPT_CAP_WB |
 		    EPT_CAP_2M_PAGE |