Message ID | 20211120074644.729-13-jiangyifei@huawei.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add riscv kvm accel support | expand |
On 11/20/21 8:46 AM, Yifei Jiang wrote: > const VMStateDescription vmstate_riscv_cpu = { > .name = "cpu", > .version_id = 3, > .minimum_version_id = 3, > + .post_load = cpu_post_load, > .fields = (VMStateField[]) { > VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), > VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), > @@ -211,6 +221,10 @@ const VMStateDescription vmstate_riscv_cpu = { > VMSTATE_UINT64(env.mtohost, RISCVCPU), > VMSTATE_UINT64(env.timecmp, RISCVCPU), > > + VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), > + VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), > + VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), > + > VMSTATE_END_OF_LIST() > }, Can't alter VMStateDescription.fields without bumping version. If this is really kvm-only state, consider placing it into a subsection. But I worry about kvm-only state because ideally we'd be able to migrate between tcg and kvm (if only for debugging). r~
> -----Original Message----- > From: Richard Henderson [mailto:richard.henderson@linaro.org] > Sent: Sunday, November 21, 2021 6:35 AM > To: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org; > qemu-riscv@nongnu.org > Cc: bin.meng@windriver.com; limingwang (A) <limingwang@huawei.com>; > kvm@vger.kernel.org; libvir-list@redhat.com; anup.patel@wdc.com; wanbo (G) > <wanbo13@huawei.com>; Alistair.Francis@wdc.com; > kvm-riscv@lists.infradead.org; Wanghaibin (D) > <wanghaibin.wang@huawei.com>; palmer@dabbelt.com; Fanliang (EulerOS) > <fanliang@huawei.com>; Wubin (H) <wu.wubin@huawei.com> > Subject: Re: [PATCH v1 12/12] target/riscv: Support virtual time context > synchronization > > On 11/20/21 8:46 AM, Yifei Jiang wrote: > > const VMStateDescription vmstate_riscv_cpu = { > > .name = "cpu", > > .version_id = 3, > > .minimum_version_id = 3, > > + .post_load = cpu_post_load, > > .fields = (VMStateField[]) { > > VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), > > VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -211,6 > > +221,10 @@ const VMStateDescription vmstate_riscv_cpu = { > > VMSTATE_UINT64(env.mtohost, RISCVCPU), > > VMSTATE_UINT64(env.timecmp, RISCVCPU), > > > > + VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), > > + VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), > > + VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), > > + > > VMSTATE_END_OF_LIST() > > }, > > Can't alter VMStateDescription.fields without bumping version. > > If this is really kvm-only state, consider placing it into a subsection. But I > worry about kvm-only state because ideally we'd be able to migrate between > tcg and kvm (if only for debugging). > > > r~ Thanks, I will update the version in the next series and place it into a subsection. Yifei
On 11/20/21 23:34, Richard Henderson wrote: > On 11/20/21 8:46 AM, Yifei Jiang wrote: >> const VMStateDescription vmstate_riscv_cpu = { >> .name = "cpu", >> .version_id = 3, >> .minimum_version_id = 3, >> + .post_load = cpu_post_load, >> .fields = (VMStateField[]) { >> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), >> VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), >> @@ -211,6 +221,10 @@ const VMStateDescription vmstate_riscv_cpu = { >> VMSTATE_UINT64(env.mtohost, RISCVCPU), >> VMSTATE_UINT64(env.timecmp, RISCVCPU), >> + VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), >> + VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), >> + VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), >> + >> VMSTATE_END_OF_LIST() >> }, > > Can't alter VMStateDescription.fields without bumping version. > > If this is really kvm-only state, consider placing it into a > subsection. But I worry about kvm-only state because ideally we'd be > able to migrate between tcg and kvm (if only for debugging). Where is this state stored for TCG? Paolo
diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ad8248ebfd..153215549b 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -164,10 +164,20 @@ static const VMStateDescription vmstate_pointermasking = { } }; +static int cpu_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + env->kvm_timer_dirty = true; + return 0; +} + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 3, .minimum_version_id = 3, + .post_load = cpu_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -211,6 +221,10 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT64(env.mtohost, RISCVCPU), VMSTATE_UINT64(env.timecmp, RISCVCPU), + VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), + VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), + VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), + VMSTATE_END_OF_LIST() }, .subsections = (const VMStateDescription * []) {