diff mbox series

[kvm-unit-tests,RFC,06/17] x86 TDX: Simulate single step on #VE handled instruction

Message ID 20220303071907.650203-7-zhenzhong.duan@intel.com (mailing list archive)
State New, archived
Headers show
Series X86: TDX framework support | expand

Commit Message

Duan, Zhenzhong March 3, 2022, 7:18 a.m. UTC 
According to TDX spec, specific instructions are simulated in #VE
handler, such as cpuid(0xb) and wrmsr(0x1a0).

To avoid missing single step on these instructions, we have to
simulate #DB processing in #VE handler.

Move declaration of do_handle_exception() in header file, so it can
be used in #VE handler for #DB processing.

Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Yu Zhang <yu.c.zhang@intel.com>
---
 lib/x86/desc.c | 5 -----
 lib/x86/desc.h | 4 ++++
 lib/x86/tdx.c  | 9 ++++++++-
 3 files changed, 12 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/lib/x86/desc.c b/lib/x86/desc.c
index 52eb4152385a..78f4b6576888 100644
--- a/lib/x86/desc.c
+++ b/lib/x86/desc.c
@@ -51,11 +51,6 @@  struct descriptor_table_ptr gdt_descr = {
 	.base = (unsigned long)gdt,
 };
 
-#ifndef __x86_64__
-__attribute__((regparm(1)))
-#endif
-void do_handle_exception(struct ex_regs *regs);
-
 void set_idt_entry(int vec, void *addr, int dpl)
 {
     idt_entry_t *e = &boot_idt[vec];
diff --git a/lib/x86/desc.h b/lib/x86/desc.h
index 068ec2394df9..2cd819574374 100644
--- a/lib/x86/desc.h
+++ b/lib/x86/desc.h
@@ -222,6 +222,10 @@  unsigned exception_vector(void);
 int write_cr4_checking(unsigned long val);
 unsigned exception_error_code(void);
 bool exception_rflags_rf(void);
+#ifndef __x86_64__
+__attribute__((regparm(1)))
+#endif
+void do_handle_exception(struct ex_regs *regs);
 void set_idt_entry(int vec, void *addr, int dpl);
 void set_idt_sel(int vec, u16 sel);
 void set_idt_dpl(int vec, u16 dpl);
diff --git a/lib/x86/tdx.c b/lib/x86/tdx.c
index 1fc8030c34fa..2b2e3164be33 100644
--- a/lib/x86/tdx.c
+++ b/lib/x86/tdx.c
@@ -365,8 +365,15 @@  static bool tdx_handle_virtualization_exception(struct ex_regs *regs,
 	}
 
 	/* After successful #VE handling, move the IP */
-	if (ret)
+	if (ret) {
 		regs->rip += ve->instr_len;
+		/* Simulate single step on simulated instruction */
+		if (regs->rflags & X86_EFLAGS_TF) {
+			regs->vector = DB_VECTOR;
+			write_dr6(read_dr6() | (1 << 14));
+			do_handle_exception(regs);
+		}
+	}
 	else
 		ret = tdx_check_exception_table(regs);