diff mbox series

[kvm-unit-tests,RFC,05/17] x86 TDX: bypass wrmsr simulation on some specific MSRs

Message ID 20220303071907.650203-6-zhenzhong.duan@intel.com (mailing list archive)
State New, archived
Headers show
Series X86: TDX framework support | expand

Commit Message

Duan, Zhenzhong March 3, 2022, 7:18 a.m. UTC 
In TDX scenario, some MSRs are initialized with expected value
and not expected to be changed in TD-guest.

Writing to MSR_IA32_TSC, MSR_IA32_APICBASE, MSR_EFER in TD-guest
triggers #VE. In #VE handler these MSR access are simulated with
tdvmcall. But in current TDX host side implementation, they are
bypassed and return failure.

In order to let test cases touching those MSRs run smoothly, bypass
writing to those MSRs in #VE handler just like writing succeed.

Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Yu Zhang <yu.c.zhang@intel.com>
---
 lib/x86/tdx.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/lib/x86/tdx.c b/lib/x86/tdx.c
index 62e0e2842822..1fc8030c34fa 100644
--- a/lib/x86/tdx.c
+++ b/lib/x86/tdx.c
@@ -311,6 +311,18 @@  static bool tdx_get_ve_info(struct ve_info *ve)
 	return true;
 }
 
+static bool tdx_is_bypassed_msr(u32 index)
+{
+	switch (index) {
+	case MSR_IA32_TSC:
+	case MSR_IA32_APICBASE:
+	case MSR_EFER:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static bool tdx_handle_virtualization_exception(struct ex_regs *regs,
 		struct ve_info *ve)
 {
@@ -338,7 +350,8 @@  static bool tdx_handle_virtualization_exception(struct ex_regs *regs,
 		}
 		break;
 	case EXIT_REASON_MSR_WRITE:
-		ret = tdx_write_msr(regs->rcx, regs->rax, regs->rdx);
+		if (!tdx_is_bypassed_msr(regs->rcx))
+			ret = tdx_write_msr(regs->rcx, regs->rax, regs->rdx);
 		break;
 	case EXIT_REASON_CPUID:
 		ret = tdx_handle_cpuid(regs);