| Message ID | 20230202124230.295997-9-lawrence.hunter@codethink.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add RISC-V vector cryptography extensions | expand |
On Thu, 2 Feb 2023 at 13:42, Lawrence Hunter <lawrence.hunter@codethink.co.uk> wrote: > > From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> > > Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> > --- > target/riscv/helper.h | 4 ++++ > target/riscv/insn32.decode | 1 + > target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + > target/riscv/vcrypto_helper.c | 10 ++++++++++ > 4 files changed, 16 insertions(+) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index c94627d8a4..c980d52828 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -1163,6 +1163,10 @@ DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) > DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) > DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) > > +DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32) > +DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32) > +DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32) > +DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32) > DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) > DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) > DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 782632a165..342199abc0 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -903,3 +903,4 @@ vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm > vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm > vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm > vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm > +vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm > diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc > index 591980459a..18b362db92 100644 > --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc > +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc > @@ -154,3 +154,4 @@ static bool vxrev8_check(DisasContext *s, arg_rmr *a) > } > > GEN_OPIV_TRANS(vbrev8_v, vxrev8_check) > +GEN_OPIV_TRANS(vrev8_v, vxrev8_check) > diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c > index 303a656141..b09fe5fa2a 100644 > --- a/target/riscv/vcrypto_helper.c > +++ b/target/riscv/vcrypto_helper.c > @@ -125,3 +125,13 @@ GEN_VEXT_V(vbrev8_v_b, 1) > GEN_VEXT_V(vbrev8_v_h, 2) > GEN_VEXT_V(vbrev8_v_w, 4) > GEN_VEXT_V(vbrev8_v_d, 8) > + > +#define DO_VREV8_B(a) (a) > +RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_VREV8_B) Let's call it what it is: "DO_COPY" or "DO_IDENTITY" ... > +RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16) > +RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32) > +RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64) > +GEN_VEXT_V(vrev8_v_b, 1) > +GEN_VEXT_V(vrev8_v_h, 2) > +GEN_VEXT_V(vrev8_v_w, 4) > +GEN_VEXT_V(vrev8_v_d, 8) > -- > 2.39.1 >
diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c94627d8a4..c980d52828 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1163,6 +1163,10 @@ DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 782632a165..342199abc0 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -903,3 +903,4 @@ vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm +vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index 591980459a..18b362db92 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -154,3 +154,4 @@ static bool vxrev8_check(DisasContext *s, arg_rmr *a) } GEN_OPIV_TRANS(vbrev8_v, vxrev8_check) +GEN_OPIV_TRANS(vrev8_v, vxrev8_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 303a656141..b09fe5fa2a 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -125,3 +125,13 @@ GEN_VEXT_V(vbrev8_v_b, 1) GEN_VEXT_V(vbrev8_v_h, 2) GEN_VEXT_V(vbrev8_v_w, 4) GEN_VEXT_V(vbrev8_v_d, 8) + +#define DO_VREV8_B(a) (a) +RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_VREV8_B) +RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16) +RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32) +RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64) +GEN_VEXT_V(vrev8_v_b, 1) +GEN_VEXT_V(vrev8_v_h, 2) +GEN_VEXT_V(vrev8_v_w, 4) +GEN_VEXT_V(vrev8_v_d, 8)