| Message ID | 20230328050231.3008531-3-seanjc@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/msr: Add tests for command MSRs | expand |
On Tue, Mar 28, 2023 at 7:02 AM Sean Christopherson <seanjc@google.com> wrote: > > Add test coverage to verify MSR_IA32_PRED_CMD is write-only, that it can > be written with '0' (nop command) and '1' (IBPB command) when IBPB is > supported by the CPU (SPEC_CTRL on Intel, IBPB on AMD), and that writing > any other bit (1-63) triggers a #GP due to the bits/commands being > reserved. > > Signed-off-by: Sean Christopherson <seanjc@google.com> I have a machine here (run-of-the-mill Skylake Xeon Gold) where MSR_IA32_PRED_CMD does not fail for bits 1-63, so I am dropping that bit. Paolo > --- > x86/msr.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/x86/msr.c b/x86/msr.c > index 97cf5987..13cb6391 100644 > --- a/x86/msr.c > +++ b/x86/msr.c > @@ -85,6 +85,15 @@ static void test_msr_rw(u32 msr, const char *name, unsigned long long val) > __test_msr_rw(msr, name, val, 0); > } > > +static void test_wrmsr(u32 msr, const char *name, unsigned long long val) > +{ > + unsigned char vector = wrmsr_safe(msr, val); > + > + report(!vector, > + "Expected success on WRSMR(%s, 0x%llx), got vector %d", > + name, val, vector); > +} > + > static void test_wrmsr_fault(u32 msr, const char *name, unsigned long long val) > { > unsigned char vector = wrmsr_safe(msr, val); > @@ -271,6 +280,23 @@ static void test_x2apic_msrs(void) > __test_x2apic_msrs(true); > } > > +static void test_cmd_msrs(void) > +{ > + int i; > + > + test_rdmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD"); > + if (this_cpu_has(X86_FEATURE_SPEC_CTRL) || > + this_cpu_has(X86_FEATURE_AMD_IBPB)) { > + test_wrmsr(MSR_IA32_PRED_CMD, "PRED_CMD", 0); > + test_wrmsr(MSR_IA32_PRED_CMD, "PRED_CMD", PRED_CMD_IBPB); > + } else { > + test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", 0); > + test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", PRED_CMD_IBPB); > + } > + for (i = 1; i < 64; i++) > + test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", BIT_ULL(i)); > +} > + > int main(int ac, char **av) > { > /* > @@ -283,6 +309,7 @@ int main(int ac, char **av) > test_misc_msrs(); > test_mce_msrs(); > test_x2apic_msrs(); > + test_cmd_msrs(); > } > > return report_summary(); > -- > 2.40.0.348.gf938b09366-goog >
diff --git a/x86/msr.c b/x86/msr.c index 97cf5987..13cb6391 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -85,6 +85,15 @@ static void test_msr_rw(u32 msr, const char *name, unsigned long long val) __test_msr_rw(msr, name, val, 0); } +static void test_wrmsr(u32 msr, const char *name, unsigned long long val) +{ + unsigned char vector = wrmsr_safe(msr, val); + + report(!vector, + "Expected success on WRSMR(%s, 0x%llx), got vector %d", + name, val, vector); +} + static void test_wrmsr_fault(u32 msr, const char *name, unsigned long long val) { unsigned char vector = wrmsr_safe(msr, val); @@ -271,6 +280,23 @@ static void test_x2apic_msrs(void) __test_x2apic_msrs(true); } +static void test_cmd_msrs(void) +{ + int i; + + test_rdmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD"); + if (this_cpu_has(X86_FEATURE_SPEC_CTRL) || + this_cpu_has(X86_FEATURE_AMD_IBPB)) { + test_wrmsr(MSR_IA32_PRED_CMD, "PRED_CMD", 0); + test_wrmsr(MSR_IA32_PRED_CMD, "PRED_CMD", PRED_CMD_IBPB); + } else { + test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", 0); + test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", PRED_CMD_IBPB); + } + for (i = 1; i < 64; i++) + test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", BIT_ULL(i)); +} + int main(int ac, char **av) { /* @@ -283,6 +309,7 @@ int main(int ac, char **av) test_misc_msrs(); test_mce_msrs(); test_x2apic_msrs(); + test_cmd_msrs(); } return report_summary();
Add test coverage to verify MSR_IA32_PRED_CMD is write-only, that it can be written with '0' (nop command) and '1' (IBPB command) when IBPB is supported by the CPU (SPEC_CTRL on Intel, IBPB on AMD), and that writing any other bit (1-63) triggers a #GP due to the bits/commands being reserved. Signed-off-by: Sean Christopherson <seanjc@google.com> --- x86/msr.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)