| Message ID | 20240216030128.29154-2-ankita@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | vfio/nvgrace-gpu: Add vfio pci variant module for grace hopper | expand |
On 16/02/2024 5:01, ankita@nvidia.com wrote: > From: Ankit Agrawal <ankita@nvidia.com> > > do_io_rw() is used to read/write to the device MMIO. The grace hopper > VFIO PCI variant driver require this functionality to read/write to > its memory. > > Rename this as vfio_pci_core functions and export as GPL. > > Reviewed-by: Kevin Tian <kevin.tian@intel.com> > Signed-off-by: Ankit Agrawal <ankita@nvidia.com> > --- > drivers/vfio/pci/vfio_pci_rdwr.c | 16 +++++++++------- > include/linux/vfio_pci_core.h | 5 ++++- > 2 files changed, 13 insertions(+), 8 deletions(-) > > diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c > index 07fea08ea8a2..03b8f7ada1ac 100644 > --- a/drivers/vfio/pci/vfio_pci_rdwr.c > +++ b/drivers/vfio/pci/vfio_pci_rdwr.c > @@ -96,10 +96,10 @@ VFIO_IOREAD(32) > * reads with -1. This is intended for handling MSI-X vector tables and > * leftover space for ROM BARs. > */ > -static ssize_t do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, > - void __iomem *io, char __user *buf, > - loff_t off, size_t count, size_t x_start, > - size_t x_end, bool iswrite) > +ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, > + void __iomem *io, char __user *buf, > + loff_t off, size_t count, size_t x_start, > + size_t x_end, bool iswrite) > { > ssize_t done = 0; > int ret; > @@ -201,6 +201,7 @@ static ssize_t do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, > > return done; > } > +EXPORT_SYMBOL_GPL(vfio_pci_core_do_io_rw); > > int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar) > { > @@ -279,8 +280,8 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, > x_end = vdev->msix_offset + vdev->msix_size; > } > > - done = do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, > - count, x_start, x_end, iswrite); > + done = vfio_pci_core_do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, > + count, x_start, x_end, iswrite); > > if (done >= 0) > *ppos += done; > @@ -348,7 +349,8 @@ ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vdev, char __user *buf, > * probing, so we don't currently worry about access in relation > * to the memory enable bit in the command register. > */ > - done = do_io_rw(vdev, false, iomem, buf, off, count, 0, 0, iswrite); > + done = vfio_pci_core_do_io_rw(vdev, false, iomem, buf, off, count, > + 0, 0, iswrite); > > vga_put(vdev->pdev, rsrc); > > diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h > index 85e84b92751b..cf9480a31f3e 100644 > --- a/include/linux/vfio_pci_core.h > +++ b/include/linux/vfio_pci_core.h > @@ -130,7 +130,10 @@ void vfio_pci_core_finish_enable(struct vfio_pci_core_device *vdev); > int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar); > pci_ers_result_t vfio_pci_core_aer_err_detected(struct pci_dev *pdev, > pci_channel_state_t state); > - > +ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, > + void __iomem *io, char __user *buf, > + loff_t off, size_t count, size_t x_start, > + size_t x_end, bool iswrite); > #define VFIO_IOWRITE_DECLATION(size) \ > int vfio_pci_core_iowrite##size(struct vfio_pci_core_device *vdev, \ > bool test_mem, u##size val, void __iomem *io); Reviewed-by: Yishai Hadas <yishaih@nvidia.com>
diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index 07fea08ea8a2..03b8f7ada1ac 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -96,10 +96,10 @@ VFIO_IOREAD(32) * reads with -1. This is intended for handling MSI-X vector tables and * leftover space for ROM BARs. */ -static ssize_t do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, - void __iomem *io, char __user *buf, - loff_t off, size_t count, size_t x_start, - size_t x_end, bool iswrite) +ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, + void __iomem *io, char __user *buf, + loff_t off, size_t count, size_t x_start, + size_t x_end, bool iswrite) { ssize_t done = 0; int ret; @@ -201,6 +201,7 @@ static ssize_t do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, return done; } +EXPORT_SYMBOL_GPL(vfio_pci_core_do_io_rw); int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar) { @@ -279,8 +280,8 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, x_end = vdev->msix_offset + vdev->msix_size; } - done = do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, - count, x_start, x_end, iswrite); + done = vfio_pci_core_do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, + count, x_start, x_end, iswrite); if (done >= 0) *ppos += done; @@ -348,7 +349,8 @@ ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vdev, char __user *buf, * probing, so we don't currently worry about access in relation * to the memory enable bit in the command register. */ - done = do_io_rw(vdev, false, iomem, buf, off, count, 0, 0, iswrite); + done = vfio_pci_core_do_io_rw(vdev, false, iomem, buf, off, count, + 0, 0, iswrite); vga_put(vdev->pdev, rsrc); diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 85e84b92751b..cf9480a31f3e 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -130,7 +130,10 @@ void vfio_pci_core_finish_enable(struct vfio_pci_core_device *vdev); int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar); pci_ers_result_t vfio_pci_core_aer_err_detected(struct pci_dev *pdev, pci_channel_state_t state); - +ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, + void __iomem *io, char __user *buf, + loff_t off, size_t count, size_t x_start, + size_t x_end, bool iswrite); #define VFIO_IOWRITE_DECLATION(size) \ int vfio_pci_core_iowrite##size(struct vfio_pci_core_device *vdev, \ bool test_mem, u##size val, void __iomem *io);