| Message ID | 20240506053020.3911940-39-mizhang@google.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Mediated Passthrough vPMU 2.0 for x86 | expand |
On Mon, May 06, 2024 at 05:30:03AM +0000, Mingwei Zhang wrote: > From: Xiong Zhang <xiong.y.zhang@linux.intel.com> > > perf subsystem should stop and restart all the perf events at the host > level when entering and leaving passthrough PMU respectively. So invoke > the perf API at PMU context switch functions. > > Signed-off-by: Xiong Zhang <xiong.y.zhang@linux.intel.com> > Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> > --- > arch/x86/events/core.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index f5a043410614..6fe467bca809 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -705,6 +705,8 @@ void x86_perf_guest_enter(u32 guest_lvtpc) > { > lockdep_assert_irqs_disabled(); > > + perf_guest_enter(); > + > apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | > (guest_lvtpc & APIC_LVT_MASKED)); > } > @@ -715,6 +717,8 @@ void x86_perf_guest_exit(void) > lockdep_assert_irqs_disabled(); > > apic_write(APIC_LVTPC, APIC_DM_NMI); > + > + perf_guest_exit(); > } > EXPORT_SYMBOL_GPL(x86_perf_guest_exit); *sigh*.. why does this patch exist? Please merge with the one that introduces these functions. This is making review really hard.
On 5/7/2024 5:39 PM, Peter Zijlstra wrote: > On Mon, May 06, 2024 at 05:30:03AM +0000, Mingwei Zhang wrote: >> From: Xiong Zhang <xiong.y.zhang@linux.intel.com> >> >> perf subsystem should stop and restart all the perf events at the host >> level when entering and leaving passthrough PMU respectively. So invoke >> the perf API at PMU context switch functions. >> >> Signed-off-by: Xiong Zhang <xiong.y.zhang@linux.intel.com> >> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> >> --- >> arch/x86/events/core.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c >> index f5a043410614..6fe467bca809 100644 >> --- a/arch/x86/events/core.c >> +++ b/arch/x86/events/core.c >> @@ -705,6 +705,8 @@ void x86_perf_guest_enter(u32 guest_lvtpc) >> { >> lockdep_assert_irqs_disabled(); >> >> + perf_guest_enter(); >> + >> apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | >> (guest_lvtpc & APIC_LVT_MASKED)); >> } >> @@ -715,6 +717,8 @@ void x86_perf_guest_exit(void) >> lockdep_assert_irqs_disabled(); >> >> apic_write(APIC_LVTPC, APIC_DM_NMI); >> + >> + perf_guest_exit(); >> } >> EXPORT_SYMBOL_GPL(x86_perf_guest_exit); > *sigh*.. why does this patch exist? Please merge with the one that > introduces these functions. > > This is making review really hard. Sure. we would adjust the patches sequence. Thanks.
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index f5a043410614..6fe467bca809 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -705,6 +705,8 @@ void x86_perf_guest_enter(u32 guest_lvtpc) { lockdep_assert_irqs_disabled(); + perf_guest_enter(); + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | (guest_lvtpc & APIC_LVT_MASKED)); } @@ -715,6 +717,8 @@ void x86_perf_guest_exit(void) lockdep_assert_irqs_disabled(); apic_write(APIC_LVTPC, APIC_DM_NMI); + + perf_guest_exit(); } EXPORT_SYMBOL_GPL(x86_perf_guest_exit);