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[v2,04/54] x86/msr: Define PerfCntrGlobalStatusSet register

Message ID	20240506053020.3911940-5-mizhang@google.com (mailing list archive)
State	New
Headers	show Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B5544AEF5 for <kvm@vger.kernel.org>; Mon, 6 May 2024 05:30:35 +0000 (UTC) Reply-To: Mingwei Zhang <mizhang@google.com> Date: Mon, 6 May 2024 05:29:29 +0000 In-Reply-To: <20240506053020.3911940-1-mizhang@google.com> Precedence: bulk Mime-Version: 1.0 References: <20240506053020.3911940-1-mizhang@google.com> Message-ID: <20240506053020.3911940-5-mizhang@google.com> Subject: [PATCH v2 04/54] x86/msr: Define PerfCntrGlobalStatusSet register From: Mingwei Zhang <mizhang@google.com> To: Sean Christopherson <seanjc@google.com>, Paolo Bonzini <pbonzini@redhat.com>, Xiong Zhang <xiong.y.zhang@intel.com>, Dapeng Mi <dapeng1.mi@linux.intel.com>, Kan Liang <kan.liang@intel.com>, Zhenyu Wang <zhenyuw@linux.intel.com>, Manali Shukla <manali.shukla@amd.com>, Sandipan Das <sandipan.das@amd.com> Cc: Jim Mattson <jmattson@google.com>, Stephane Eranian <eranian@google.com>, Ian Rogers <irogers@google.com>, Namhyung Kim <namhyung@kernel.org>, Mingwei Zhang <mizhang@google.com>, gce-passthrou-pmu-dev@google.com, Samantha Alt <samantha.alt@intel.com>, Zhiyuan Lv <zhiyuan.lv@intel.com>, Yanfei Xu <yanfei.xu@intel.com>, maobibo <maobibo@loongson.cn>, Like Xu <like.xu.linux@gmail.com>, Peter Zijlstra <peterz@infradead.org>, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Type: text/plain; charset="UTF-8"
Series	Mediated Passthrough vPMU 2.0 for x86 \| expand [v2,00/54] Mediated Passthrough vPMU 2.0 for x86 [v2,01/54] KVM: x86/pmu: Set enable bits for GP counters in PERF_GLOBAL_CTRL at "RESET" [v2,02/54] KVM: x86: Snapshot if a vCPU's vendor model is AMD vs. Intel compatible [v2,03/54] KVM: x86/pmu: Do not mask LVTPC when handling a PMI on AMD platforms [v2,04/54] x86/msr: Define PerfCntrGlobalStatusSet register [v2,05/54] x86/msr: Introduce MSR_CORE_PERF_GLOBAL_STATUS_SET [v2,06/54] perf: Support get/put passthrough PMU interfaces [v2,07/54] perf: Add generic exclude_guest support [v2,08/54] perf/x86/intel: Support PERF_PMU_CAP_PASSTHROUGH_VPMU [v2,09/54] perf: core/x86: Register a new vector for KVM GUEST PMI [v2,10/54] KVM: x86: Extract x86_set_kvm_irq_handler() function [v2,11/54] KVM: x86/pmu: Register guest pmi handler for emulated PMU [v2,12/54] perf: x86: Add x86 function to switch PMI handler [v2,13/54] perf: core/x86: Forbid PMI handler when guest own PMU [v2,14/54] perf: core/x86: Plumb passthrough PMU capability from x86_pmu to x86_pmu_cap [v2,15/54] KVM: x86/pmu: Introduce enable_passthrough_pmu module parameter [v2,16/54] KVM: x86/pmu: Plumb through pass-through PMU to vcpu for Intel CPUs [v2,17/54] KVM: x86/pmu: Always set global enable bits in passthrough mode [v2,18/54] KVM: x86/pmu: Add a helper to check if passthrough PMU is enabled [v2,19/54] KVM: x86/pmu: Add host_perf_cap and initialize it in kvm_x86_vendor_init() [v2,20/54] KVM: x86/pmu: Allow RDPMC pass through when all counters exposed to guest [v2,21/54] KVM: x86/pmu: Introduce macro PMU_CAP_PERF_METRICS [v2,22/54] KVM: x86/pmu: Introduce PMU operator to check if rdpmc passthrough allowed [v2,23/54] KVM: x86/pmu: Manage MSR interception for IA32_PERF_GLOBAL_CTRL [v2,24/54] KVM: x86/pmu: Create a function prototype to disable MSR interception [v2,25/54] KVM: x86/pmu: Add intel_passthrough_pmu_msrs() to pass-through PMU MSRs [v2,26/54] KVM: x86/pmu: Avoid legacy vPMU code when accessing global_ctrl in passthrough vPMU [v2,27/54] KVM: x86/pmu: Exclude PMU MSRs in vmx_get_passthrough_msr_slot() [v2,28/54] KVM: x86/pmu: Add counter MSR and selector MSR index into struct kvm_pmc [v2,29/54] KVM: x86/pmu: Introduce PMU operation prototypes for save/restore PMU context [v2,30/54] KVM: x86/pmu: Implement the save/restore of PMU state for Intel CPU [v2,31/54] KVM: x86/pmu: Make check_pmu_event_filter() an exported function [v2,32/54] KVM: x86/pmu: Allow writing to event selector for GP counters if event is allowed [v2,33/54] KVM: x86/pmu: Allow writing to fixed counter selector if counter is exposed [v2,34/54] KVM: x86/pmu: Switch IA32_PERF_GLOBAL_CTRL at VM boundary [v2,35/54] KVM: x86/pmu: Exclude existing vLBR logic from the passthrough PMU [v2,36/54] KVM: x86/pmu: Switch PMI handler at KVM context switch boundary [v2,37/54] KVM: x86/pmu: Grab x86 core PMU for passthrough PMU VM [v2,38/54] KVM: x86/pmu: Call perf_guest_enter() at PMU context switch [v2,39/54] KVM: x86/pmu: Add support for PMU context switch at VM-exit/enter [v2,40/54] KVM: x86/pmu: Introduce PMU operator to increment counter [v2,41/54] KVM: x86/pmu: Introduce PMU operator for setting counter overflow [v2,42/54] KVM: x86/pmu: Implement emulated counter increment for passthrough PMU [v2,43/54] KVM: x86/pmu: Update pmc_{read,write}_counter() to disconnect perf API [v2,44/54] KVM: x86/pmu: Disconnect counter reprogram logic from passthrough PMU [v2,45/54] KVM: nVMX: Add nested virtualization support for passthrough PMU [v2,46/54] perf/x86/amd/core: Set passthrough capability for host [v2,47/54] KVM: x86/pmu/svm: Set passthrough capability for vcpus [v2,48/54] KVM: x86/pmu/svm: Set enable_passthrough_pmu module parameter [v2,49/54] KVM: x86/pmu/svm: Allow RDPMC pass through when all counters exposed to guest [v2,50/54] KVM: x86/pmu/svm: Implement callback to disable MSR interception [v2,51/54] KVM: x86/pmu/svm: Set GuestOnly bit and clear HostOnly bit when guest write to event sel… [v2,52/54] KVM: x86/pmu/svm: Add registers to direct access list [v2,53/54] KVM: x86/pmu/svm: Implement handlers to save and restore context [v2,54/54] KVM: x86/pmu/svm: Wire up PMU filtering functionality for passthrough PMU

Commit Message

Mingwei Zhang May 6, 2024, 5:29 a.m. UTC

From: Sandipan Das <sandipan.das@amd.com>

Define PerfCntrGlobalStatusSet (MSR 0xc0000303) as it is required by
passthrough PMU to set the overflow bits of PerfCntrGlobalStatus
(MSR 0xc0000300).

When using passthrough PMU, it is necessary to restore the guest state
of the overflow bits. Since PerfCntrGlobalStatus is read-only, this is
done by writing to PerfCntrGlobalStatusSet instead.

The register is available on AMD processors where the PerfMonV2 feature
bit of CPUID leaf 0x80000022 EAX is set.

Signed-off-by: Sandipan Das <sandipan.das@amd.com>
---
 arch/x86/include/asm/msr-index.h | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 05956bd8bacf..ed9e3e8a57d6 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -675,6 +675,7 @@ 
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302
+#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET	0xc0000303
 
 /* AMD Last Branch Record MSRs */
 #define MSR_AMD64_LBR_SELECT			0xc000010e