| Message ID | 2f3c1207f66f44fdd2f3eb0809d552f5632e4b41.1637799475.git.isaku.yamahata@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: X86: TDX support | expand |
On Wed, Nov 24 2021 at 16:20, isaku yamahata wrote: > From: Sean Christopherson <sean.j.christopherson@intel.com> > > Move the guts of vmx_cache_reg() to vt_cache_reg() in preparation for > reusing the bulk of the code for TDX, which can access guest state for > debug TDs. > > Use kvm_x86_ops.cache_reg() in ept_update_paging_mode_cr0() rather than > trying to expose vt_cache_reg() to vmx.c, even though it means taking a > retpoline. The code runs if and only if EPT is enabled but unrestricted > guest. This sentence does not parse because it's not a proper sentence. > Only one generation of CPU, Nehalem, supports EPT but not > unrestricted guest, and disabling unrestricted guest without also > disabling EPT is, to put it bluntly, dumb. This one is only significantly better and lacks an explanation what this means for the dumb case. Thanks, tglx
On 11/25/21 21:11, Thomas Gleixner wrote: >> >> Use kvm_x86_ops.cache_reg() in ept_update_paging_mode_cr0() rather than >> trying to expose vt_cache_reg() to vmx.c, even though it means taking a >> retpoline. The code runs if and only if EPT is enabled but unrestricted >> guest. > This sentence does not parse because it's not a proper sentence. > >> Only one generation of CPU, Nehalem, supports EPT but not >> unrestricted guest, and disabling unrestricted guest without also >> disabling EPT is, to put it bluntly, dumb. > This one is only significantly better and lacks an explanation what this > means for the dumb case. Well, it means a retpoline (see paragraph before). However, I'm not sure why it one wouldn't create a vt.h header with all vt_* functions. Paolo
On Thu, Nov 25, 2021, Paolo Bonzini wrote: > On 11/25/21 21:11, Thomas Gleixner wrote: > > > > > > Use kvm_x86_ops.cache_reg() in ept_update_paging_mode_cr0() rather than > > > trying to expose vt_cache_reg() to vmx.c, even though it means taking a > > > retpoline. The code runs if and only if EPT is enabled but unrestricted > > > guest. > > This sentence does not parse because it's not a proper sentence. Heh, supposed to be "... but unrestricted guest is disabled". > > > Only one generation of CPU, Nehalem, supports EPT but not > > > unrestricted guest, and disabling unrestricted guest without also > > > disabling EPT is, to put it bluntly, dumb. > > This one is only significantly better and lacks an explanation what this > > means for the dumb case. > > Well, it means a retpoline (see paragraph before). No, the point being made is that, on a CPU that supports Unrestricted Guest (UG), disabling UG without disabling EPT is really, really stupid. UG requires EPT, so disabling EPT _and_ UG is reasonable as there are scenarios where using shadow paging is desirable. But inentionally disabling UG and enabling EPT makes no sense. It forces KVM to emulate non-trivial amounts of guest code and has zero benefits for anything other than testing KVM itself. > why it one wouldn't create a vt.h header with all vt_* functions. > > Paolo >
On 11/29/21 19:23, Sean Christopherson wrote: >>>> Only one generation of CPU, Nehalem, supports EPT but not >>>> unrestricted guest, and disabling unrestricted guest without also >>>> disabling EPT is, to put it bluntly, dumb. >>> This one is only significantly better and lacks an explanation what this >>> means for the dumb case. >> Well, it means a retpoline (see paragraph before). > > No, the point being made is that, on a CPU that supports Unrestricted Guest (UG), > disabling UG without disabling EPT is really, really stupid. Yes, I understand that. Thomas was asking what it means to "Move register caching logic to common code", i.e. what the consequences are. The missing words at the end of the first paragraph didn't make the connection obvious between the extra retpoline and the "dumb case". Paolo
diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index ef89ed0457d5..a0a8cc2fd600 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -339,9 +339,47 @@ static void vt_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) vmx_sync_dirty_debug_regs(vcpu); } -static void vt_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) -{ - vmx_cache_reg(vcpu, reg); +void vt_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) +{ + unsigned long guest_owned_bits; + + kvm_register_mark_available(vcpu, reg); + + switch (reg) { + case VCPU_REGS_RSP: + vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); + break; + case VCPU_REGS_RIP: + vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); + break; + case VCPU_EXREG_PDPTR: + if (enable_ept) + ept_save_pdptrs(vcpu); + break; + case VCPU_EXREG_CR0: + guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; + + vcpu->arch.cr0 &= ~guest_owned_bits; + vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits; + break; + case VCPU_EXREG_CR3: + /* + * When intercepting CR3 loads, e.g. for shadowing paging, KVM's + * CR3 is loaded into hardware, not the guest's CR3. + */ + if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING)) + vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); + break; + case VCPU_EXREG_CR4: + guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; + + vcpu->arch.cr4 &= ~guest_owned_bits; + vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits; + break; + default: + KVM_BUG_ON(1, vcpu->kvm); + break; + } } static unsigned long vt_get_rflags(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 8b2e57de6627..98710b578b28 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2230,49 +2230,6 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) return ret; } -void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) -{ - unsigned long guest_owned_bits; - - kvm_register_mark_available(vcpu, reg); - - switch (reg) { - case VCPU_REGS_RSP: - vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); - break; - case VCPU_REGS_RIP: - vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); - break; - case VCPU_EXREG_PDPTR: - if (enable_ept) - ept_save_pdptrs(vcpu); - break; - case VCPU_EXREG_CR0: - guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; - - vcpu->arch.cr0 &= ~guest_owned_bits; - vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits; - break; - case VCPU_EXREG_CR3: - /* - * When intercepting CR3 loads, e.g. for shadowing paging, KVM's - * CR3 is loaded into hardware, not the guest's CR3. - */ - if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING)) - vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); - break; - case VCPU_EXREG_CR4: - guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; - - vcpu->arch.cr4 &= ~guest_owned_bits; - vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits; - break; - default: - KVM_BUG_ON(1, vcpu->kvm); - break; - } -} - __init int vmx_disabled_by_bios(void) { return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || @@ -3012,7 +2969,7 @@ void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) * KVM's CR3 is installed. */ if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) - vmx_cache_reg(vcpu, VCPU_EXREG_CR3); + vt_cache_reg(vcpu, VCPU_EXREG_CR3); /* * When running with EPT but not unrestricted guest, KVM must diff --git a/arch/x86/kvm/vmx/x86_ops.h b/arch/x86/kvm/vmx/x86_ops.h index f04b30f1b72d..c49d6f9f36fd 100644 --- a/arch/x86/kvm/vmx/x86_ops.h +++ b/arch/x86/kvm/vmx/x86_ops.h @@ -9,6 +9,7 @@ #include "x86.h" extern struct kvm_x86_ops vt_x86_ops __initdata; +void vt_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg); __init int vmx_disabled_by_bios(void); int __init vmx_check_processor_compat(void);